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 OmniPHY Inc 
Part Number : OMNI_DDR4_TSMC28
Short Desc. : Silicon Proven on a customer SOC - DDR4 Combo PHY supporting DDR3L, DDR3U, LPDDR3, LPDDR2
Overview :

JEDEC compliant to DDR4, DDR3L/U, LPDDR3, LPDDR2 with DFI 2.1 and 2.0 controller interface, and includes DIMM support. The DDR PHY has the richest feature set available on the market - combining great signal integrity and yield with ease of integration and test. 

The base design is TSMC 28HPL and is easily ported to other technologies.

Benefits:

  • Architected for low latency, low-power, best-in-class
  • Allows one SoC design to use DDR3L or DDR4, whichever is cheaper, for many powered applications, and LPDDR2 or LPDDR3, whichever is cheaper, for mobile applications
  • A rich feature-set enables good signal integrity even at 3200Mb/s

Features : - DIMM and Multi-Rank Support
- Up to 3200Mbps a 72-bit interface = 28.8GB/s of maximum bandwidth
- Support 1:1, 1:2 DDR controller interface
- Byte Support
- External and internal VREF generation, VREF calibration and training
- CT and OD termination support
- Programmable read and write pre-ambles
- Full support for DFI PHY training types and interface operatin modes
- Data bus inversion, trained Vref, bank groups, write CRC
- LPDDR2 and LPDDR3 multiplexes the control and address lines onto a 10-bit double data rate CA bus
Categories :
Maturity : Pre-Silicon
Portability :
Type :
 Hard IP 
Foundry :
TSMC
Nodes :
28nm
40nm

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