OmniPHY Inc 
Part Number : OMNI_101001000_TSMC28
Short Desc. : 10/100/1000 Gigabit Ethernet PHY - TSMC 28nm HPM
Overview :

The IP is low-power 10BASE-T/100BASE-TX/1000BASE-T Ethernet physical layer (PHY) transceiver with variable I/O voltage. The IP is designed and optimized in TSMC's 28nm node. 

It can be configured to interface with a controller through MII/RMII/SMII interfaces. The PHY is ideal for use in set-top boxes, gaming consoles, instrumentation, DVR's, wireless access points, digital TV's, industrial applications and many more! 

Area/Power available under NDA - leading edge specifications are achieved for this mature standard.


  • Optimized in 28nm, lowest area and power on the market
  • Supporting temperature range of -40C to 125C!
  • Perfect mix of analog and digital lends itself to robustness, portability, and performance
  • Multiple clock options
  • Stand-alone core

Features : - 10BASE-T/100BASE-TX/1000BASE-T Ethernet physical layer (PHY)
- Integrated PMD sublayer featuring adaptive equalization and baseline wander compensation according to ANSI X3.T12
- IEEE 802.3u MII, IEEE 802.3z GMII, RGMII version 1.3 interfaces
- IEEE 802.3u Auto-Negotiation and Parallel Detection
- Fully Auto-Negotiates between 1000 Mb/s, 100 Mb/s, and 10 Mb/s full duplex and half duplex devices
- On-Chip TDR/Cable-Diagnostic
- Flexible configurations for LED status indicators - LED support for activity, full / half duplex, link1000, link100 and link10
- Supports 25 MHz reference clock
- Requires only two power supplies, 1.8 V (core and analog) and 2.5 V (analog and I/O). 3.3V is supported as an alternative supply for I/O voltage
- Supports Auto-MDIX at 10, 100 and 1000 Mb/s
- Full set of power down modes
Categories :
Portability :
Type :
 Hard IP 
Foundry :
Nodes :

Deliverables : - GDSII - compliant with DFM
- .LEF
- LIBERTY files for timing closure
- Verilog
- Netlist
- Extensive documentation
S2C: FPGA Base prototyping- Download white paper

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