Part Number : dwc_ddr4_ddr3_phy_tsmc16ffpgl
Short Desc. : DDR4/3 PHY - TSMC16FF+GL
Overview :

The Synopsys DesignWare® DDR4/3 PHY is a complete physical layer IP interface (PHY) solution for enterprise-class ASIC, ASSP, and system-on-chip (SoC) applications requiring high-performance DDR4/DDR3/DDR3L SDRAM interfaces operating at up to 3200 Mbps. The DesignWare DDR4/3 PHY is ideal for systems that require high-speed DDR3/4 performance requiring high capacity memory solutions, typically using registered and load reduced memory modules (RDIMMs and LRDIMMs) with up to 16 ranks. Direct SDRAM on PCB systems are also supported.

Optimized for high performance, low latency, low area, low power, and ease of integration, the DesignWare DDR4/3 PHY is provided as a hard DDR PHY that is primarily delivered as GDSII including integrated application-specific DDR4/3 I/Os. Supporting the GDSII-based PHY is the RTL-based PHY Utility Block (PUB) that includes PHY control features such as read/write leveling, data eye training, per-bit data deskew control, PVT compensation, and support for production testing of the DDR4/3 PHY. The PUB also includes an embedded calibration processor to execute hardware-assisted, firmware-based training algorithms. The DDR4/3 PHY includes a DFI 4.0 interface to the memory controller and can be combined with Synopsys’ Enhanced Universal Memory (uMCTL2) or Protocol (uPCTL2) controllers for a complete DDR interface solution.

Features : Supports JEDEC standard DDR4, DDR3, and DDR3L SDRAMs High-performance DDR PHY supporting data rates up to 3200 Mbps Compatible with JEDEC compliant DDR3/4 UDIMMs and RDIMMs as well as DDR4 LRDIMMs Supports up to 16 logical ranks for high capacity memory requirements PHY independent, firmware-based training using an embedded calibration processor Supports up to 4 trained states/frequencies with <5us switching time I/O receiver decision feedback equalization and driver feed-forward equalization VT compensated delay lines for DQS centering, read/write leveling, and per bit deskew DFI 4.0-compliant controller interface Designed for rapid integration with Synopsys memory or protocol controllers for a complete DDR interface solution
Categories :
Maturity : Available On Request
Portability :
Type :
 Hard IP 
Foundry :
Nodes :
Process :

Deliverables : - Executable .run installation file which includes GDSII, LEF Files, LVS Netlists, .lib/.db Timing Models, Verilog Model, DRC/LVS Log Files, I/O IBIS Model, I/O HSPICE Netlist, Parameterized Verilog top-level PHY netlist files
- Sample Verification Environment, PHY Data Book, Physical Implementation Guide, App Notes, Verification Guide, Installation Guide, Implementation Checklist
- The PHY Utility Block is included in all but the DDR2/DDR PHYs and includes Verilog Code, Synthesis/STA constraints and scripts, Sample Verification Environment, PUBL Data Book
- DDR PHY Compiler
S2C: FPGA Base prototyping- Download white paper

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