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Cadence Design Systems, Inc.
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MIPI CSI-2 Transmitter
Our MIPI CSI ‑2 Transmitter (Tx) IP is a fully-verified configurable digital core compliant with the MIPI®Alliance Specification for Camera Serial Interface 2 (CSI‑2) version 1.1. It provides a standard, low-power, high-speed interface, and supports all primary and secondary data types defined by MIPI CSI-2 . Cadence MIPI CSI-2 Tx (Host Controller) handles CSI-2 protocols and packs input pixel data into D-PHY packet streams. It is architected to connect seamlessly to Cadence, or third-party, PPI-compliant D-PHY Lane Modules, providing a high-speed serial interface between an application or image processor and MIPI CSI-2 compliant camera sensor.
- Compliant with MIPI CSI ‑2 v1.1
- Support for all primary and secondary data formats
- Virtual Channel / Data type interleaving
- Dynamic lane distribution
- Supports ULPS on all Data Lanes
- Up to four pixel stream inputs
- Supports multiple video formats with two pixels each pixel clock
- Up to four data lanes for the D-PHY interface
- Each data lane supports up to 1.5Gbps
- Clean, readable, synthesizable Verilog RTL
- Synthesis scripts
- Documentation: integration and user guide, release notes
- Sample verification testbench with integrated BFM and monitors
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