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 Cadence Design Systems, Inc. 
Part Number : IP5021
Short Desc. : MIPI CSI-2 TX v1.1 Controller
Overview :

The Cadence Transmitter Controller IP for MIPI CSI-2 is a fully-verified configurable digital core compliant with MIPI Alliance Specification for Camera Serial Interface 2 version 1.1.  It provides a standard, low-power, high-speed interface, and supports all primary and secondary data types defined by MIPI CSI-2.
The Controller IP is engineered to quickly and easily integrate into any System-on-Chip (SoC) design, and to connect seamlessly to a Cadence, or third-party PPI-compliant D-PHY lane modules. The Cadence Transmitter Controller IP for MIPI CSI-2 IP is an ideal cost-effective, low-power solution to provide a high-speed serial interface between an application or image processor and MIPI CSI-2 compliant camera sensor.


Features : - Virtual Channel / Data type interleaving
- Dynamic lane distribution
- Support for all primary and secondary data formats
- Supports ULPS on all Data Lanes and Clock Lane
- Each lane supports up to 2.5Gbps
- Up to four data lanes for the D-PHY interface
- Up to four pixel stream inputs
Categories :
Maturity : Available on request
Portability :
Type : Soft
Deliverables : - Clear, readable, synthesizable Verilog RTL
- Synthesis scripts
- Sample Verification testbench with integrated BFM and monitors
- Documentation - Design Specification, Verification Specification and Test Plan
TrueCircuits: UltraPLL



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