Part Number : dwipk_umctl2_elpddr4phy_arc
Short Desc. : IP Prototyping Kit for DWC DDR uMCTL2 Controller on HAPS-DX7, LPDDR4 emulation MultiPHY, AXI tunnel to ARC SDP
Overview :

The DesignWare® IP Prototyping Kits for DDR uMCTL2 center around a complete, out-of-the-box reference design that consists of a validated IP configuration and necessary SoC integration logic, implemented on Synopsys’ HAPS®-DX FPGA-based prototyping system.

 With a proven reference design for the IP, designers can be instantly productive, enabling them to accelerate the integration of IP into their target SoC, optimize the IP configuration, and develop drivers and software applications with real world I/Os and hardware. The prototyping kits take advantage of Synopsys’ HAPS Developer eXpress (HAPS-DX) system to provide prototyping hardware and software automation tools. Scripts and configuration files enable fast iteration.

 The IP Prototyping Kits can be used as a physical target for early software bring-up, debug and test concurrently with SoC development. Out-of-the-box support for Linux software stack ensures that software developers are up and running instantly and can focus on the IP specific software (e.g., drivers, bootcode, firmware). The kits plugs into existing software tool chains and interfaces seamlessly with popular embedded software debuggers, providing system-wide debug and analysis capabilities.

Features : - uMCTL2 Controller: DRAM data width: 32; Single port support; DDR3 mode enabled; 8 word burst length; APB clock asynchronous to core clock
- Includes HAPS DDR3 SODIMM HT3 (single rank)
- Power management, clock reset and control block
- 32-bit AXI software development platform interface running at 150 MHz
- I2C Master to allow SPD ROM access
- Software pre-installed with Linux® OS drivers
- Pre-instrumented debug for most relevant interfaces
- ARC® AXS101 Software Development Platform
Categories :
Maturity : Avaliable
Portability :
Type :
 Hard IP 
Foundry :
Common Platform
Intel Corporation
ST Microelectronics

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