Algotronix Ltd. 
Part Number : MACSEC-40G
Short Desc. : Multiple SecY IEEE 802.1ae MACsec IP Core for 40Gbit Ethernet
Overview :

Media Access Control Security (MACsec) has been specified by the IEEE as a layer 2 security scheme. It is compatible with the revised IEEE 801.1X-2010 specification for port based Network Access Control and provides additional security for all Ethernet traffic types.

The MACSEC core is a high performance pipelined implementation of IEEE standard 802.1ae. The core is built on Algotronix' pipelined 40G implementation of the AES-GCM encryption algorithm which itself builds on our G3 AES core. Other versions of our MACSEC core support operation at 1Gbit/sec and 10Gbit/sec.


Features : - Complies with IEEE 802.1ae standard
- Multiple SecY capability
- Performance of 40Gbit/sec.
- Based on the Algotronix AES-GCM-40G product
- Supports 128 and 256 bit keys
- Targets all modern FPGA families from Xilinx and Altera and ASIC technology.
- Supplied as easily customizable portable VHDL or Verilog to allow customers to conduct their own code review in high-security applications.
- Supplied with comprehensive test bench containing a behavioral model of MACSEC developed by Algotronix.
Categories :
Tags : MACsec IEEE802.1AE
Maturity : Mature
Portability :
 FPGA Technologis 
Altera :
Stratix V
Xilinx :
Virtex-7 -2L
Virtex-7 XT
Virtex-7 XT

Type : Soft
Deliverables : - VHDL or Verilog Source code with Test Bench, Test Vectors
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers

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