Part Number : dwc_ddr4_multiphy_tsmc16ffpgl
Short Desc. : DDR4 multiPHY - TSMC 16FF+GL18
Overview :

Synopsys DesignWare® DDR4 multiPHY IP cores are mixed-signal PHY IP cores that supply the complete physical interface to JEDEC standard DDR4, DDR3, LPDDR2, and LPDDR3 SDRAM memories. The DDR4 multiPHY IP supports DDR4 SDRAM speeds from DDR4-1333 through DDR4-2400, DDR3 SDRAM speeds from DDR3-666 to DDR3-2133, LPDDR2 SDRAMs from 0 to 1066 Mbps and LPDDR3 SDRAMs from 0 to 1600 Mbps. The DDR4 multiPHY IP cores are compiled into a hard macro that is optimized for specific foundry nodes. Each DDR4 multiPHY is constructed from the following libraries of components: the application specific SSTL I/O library, a single address/command macro block, multiple byte wide data macro blocks instantiated as many times as required to accommodate the memory channel width, and separate PLL macrocells that directly abut to the address/command macro block and data macro blocks.

A key component of the DesignWare DDR4 multiPHY is the extensive in-system data training/calibration capability used to maximize the overall timing budget and improve system reliability. The DesignWare DDR4 multiPHY contains calibration circuits for read data eye training (optimizes and maintains the optimal DQS offset into the center of the read data eye), write data eye training (optimizes and maintains the optimal DQS offset into the center of the write data eye), per-bit deskew training (minimizes bit to bit timing skew for reads and writes independently), DDR3 write leveling, and DDR3 read leveling. The DDR4 multiPHY also supports per-bit deskew calibration of the address/command bus for LPDDR3 SDRAMs and VREF level training for DDR4 SDRAMs.


Features : - Support for JEDEC standard DDR4, DDR3, LPDDR2, and LPDDR3 SDRAMs
- When combined with a DesignWare DDR memory or protocol controller and verification IP, Synopsys provides a complete DDR4/DDR3/LPDDR2/LPDDR3 interface IP solution
- Compatible with the DesignWare DDR PHY Compiler
- Support for key DDR4 features including: POD_12 I/O for DDR4; Data bus inversion (DBI); VREFDQ training; CA parity
- Scalable architecture that supports data rates up to DDR4-2400
- Support for DIMMs
- Delivery of product as a hardened mixed-signal macrocell component allows precise control of timing critical delay and skew paths
- Low latency
- PHY Utility Bock (PUBM3) included as a soft IP utility that includes control features, such as write leveling and data eye training, and provides support for production testing of the DDR4 multiPHY
- DFI 3.1 compliant interface
Categories :
Tags : DDR, muktiphy
Maturity : Available on request
Portability :
Type :
 Hard IP 
Foundry :
Nodes :
Process :

Deliverables : - Executable .run installation file which includes GDSII, LEF Files, LVS Netlists, .lib/.db Timing Models, Verilog Model, DRC/LVS Log Files, I/O IBIS Model, I/O HSPICE Netlist, Parameterized Verilog top-level PHY netlist files
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