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 Algotronix Ltd. 
Part Number : AES-RNG
Short Desc. : AES Random Number Generator Core
Overview :

AES-RNG is an implementation of the latest (Nov 2014) draft of the NIST SP-800-90A standard which specifies a way of processing input from a noise source to create random bit streams suitable for use as cryptographic keys or other Critical Security Parameters.  

To support highly sensitive applications the Algotronix AES-RNG core is supplied as VHDL source code allowing customers to carry out a code review to convince themselves no ‘Trojan horse’ circuitry has been added to the core which could compromise its security.

The core is supplied with a comprehensive test bench implementing a self testing version of the synthesisable core which compares its outputs with a behavioral model developed from the pseudo-code in the standard when stimulated with random test vectors as well as using the Known Answer Tests available on the NIST website.


Features : - Implementation of the CTR-DRBG option using the AES cipher in Draft NIST SP-800- 90A, Rev 1 (Nov 2014)
- Supports Block Cipher Derivation Function (DF).
- Supports 128, 192 and 256 bit AES keys
- Targets all modern FPGA families
- Based on Algotronix AES-G3 core with a 32 bit data bus width. Can be combined with other AES-G3 based cores such as Keywrap to create a security substystem.
- Supplied as easily customizable portable VHDL to allow customers to conduct their own code review in high-security applications.
- Compilation options include implementing only required features to save area
- Supplied with comprehensive test bench implementing NIST DRBGVS tests and Algotronix developed directed random tests
Categories :
Tags : RNG, AES, DRBG
Maturity : new
Portability :
 FPGA Technologis 
Altera :
APEX 20KC
APEX 20KE
APEX II
Arria 10
Arria GX
Arria II GX
ARRIA II GZ
ARRIA V GT
ARRIA V GX
ARRIA V GZ
ARRIA V ST
ARRIA V SX
Cyclone
Cyclone II
Cyclone III
CYCLONE III LS
CYCLONE IV GX
CYCLONE V E
CYCLONE V GT
CYCLONE V GX
CYCLONE V SE
CYCLONE V ST
CYCLONE V SX
EP5C
FLEX 10K
HardCopy
HardCopy II
HARDCOPY III
HARDCOPY IV E
HARDCOPY IV GX
HardCopy Stratix
MAX II
MAX V
Stratix
Stratix GX
Stratix II
Stratix II GX
Stratix III
STRATIX III E
Stratix IV
STRATIX IV E
STRATIX IV GT
STRATIX IV GX
Stratix V
STRATIX V E
STRATIX V GS
STRATIX V GT
STRATIX V GX
Lattice :
LatticeEC/ECP
LatticeECP2
LatticeECP2M
LatticeECP3
LatticeSC
LatticeSCM
LatticeXP
LatticeXP2
Xilinx :
Artix-7
Kintex-7
Kintex-7 -2L
Spartan-3
Spartan-3 XA
Spartan-3A
Spartan-3A DSP
Spartan-3A DSP XA
Spartan-3A XA
Spartan-3AN
Spartan-3E
Spartan-3E XA
Spartan-6
Spartan-6 -1L
Spartan-6 HXT
Spartan-6 LX
Spartan-6 LXT
Spartan-6 XA
Spartan-6 XC
Virtex-4
Virtex-4 FX
Virtex-4 LX
Virtex-4 SX
Virtex-4 XA
Virtex-5
Virtex-5 FX
Virtex-5 FXT
Virtex-5 LX
Virtex-5 LXT
Virtex-5 SX
Virtex-5 SXT
Virtex-5 TXT
Virtex-6
Virtex-6 -1L
Virtex-6 CXT
Virtex-6 HXT
Virtex-6 LX
Virtex-6 LXT
Virtex-6 SXT
Virtex-7
Virtex-7 -2L
Virtex-7 XT
Virtex-7 XT
Virtex-7T
Virtex-II Pro
Zynq-7000

Type : Soft
Deliverables : - VHDL or Verilog Source code with Test Bench, Test Vectors
CST Webinar Series



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