Cadence Design Systems, Inc. 
Part Number : IP6116
Short Desc. : SD3/eMMC5.0 Soft PHY
Overview :
Cadence SD 3.0, eMMC 5.0 PHY IP is an all digital, soft PHY with a Cadence-proprietary interface for connection to a host controller. Programmable registers are accessible through the interface for setup and configuration. Cadence SD 3.0, eMMC 5.0 PHY IP supports all SD legacy modes including Default Speed, High Speed, and Ultra High Speed Phase I (UHS-I) submodes from SDR12 to SDR104,and DDR50. The eMMC support includes high-speed HS200, HS400, SDR, and DDR modes, as well as backward compatibility with previous MultiMediaCard systems.
Features : - Compliant with the SD 3.0 Physical Layer specification and JESD84-B50
- SD and eMMC removable or embedded devices
- Sample clock tuning control logic for UHS-I SDR104,and eMMC HS200
- Support for HS200 and HS400 modes
- Supports Default Speed, High Speed, and all UHS-I speeds for SD devices, and High-Speed and backwardcompatible
- SDR and DDR for eMMC devices
- Clock can be switched off for power-down mode
- Supports 1-, 4-, or 8-bit DAT bus width
Categories :
Maturity : Available on request
Portability :
Type : Soft
Deliverables : - Clean, readable, synthesizable Verilog RTL
- Synthesis and STA scripts
- Documentation: design specification, release notes
- Verification testbench with test set
- Verilog models of dummy I/O pads
CST Webinar Series
S2C: FPGA Base prototyping- Download white paper

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