In many systems-on-chip (SoC) that require analog interfaces, the 40-nm and 65-nm process nodes are the processes of choice due to their lower cost and stability when compared to more advanced nodes.
Synopsys’ high-speed DesignWare® Data Converter IP in 40-nm and 65-nm provides SoC designers with IP solutions for the high speed analog interfaces required in a large number of applications. These IP solutions are based on high-speed analog–to-digital converters (ADCs) and digital-to-analog converters (DACs) that feature small area and power consumption, making it the solution of choice for designers who need to meet challenging cost and power targets.
The DesignWare Data Converter IP includes a broad portfolio of 10-bit and 12-bit high-speed pipeline ADCs and 12-bit and 14-bit high-speed DACs, as well as 10-bit and 11-bit general-purpose ADCs and DACs and low jitter phaselocked loops (PLL), providing flexible solutions for applications such as mobile broadband wireless communication applications (LTE/LTE-A, WiFi.11n, WiFi.11ac) and digital TV reception applications. The DesignWare Data Converter IP in 40-nm and 65-nm can reach very high sampling rates with excellent dynamic performance, while processing signal bandwidth beyond 100 MHz. The IP is also ideal for home networking (G.hn) applications and for the direct conversion of high intermediate frequency (IF) signals.