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 Synopsys 
Part Number : dwc_ddr3_ddr2_phy_st28fdsoi18
Short Desc. : DDR3/2 PHY - ST 28FDSOI18
Overview :

Synopsys DesignWare® DDR3/2 PHY Cores are mixed-signal PHY IP Cores that supply the complete physical interface to JEDEC standard DDR3 and DDR2 SDRAM Memories. The DDR3/2 PHY IP supports the entire range of DDR3 SDRAM speeds, from DDR3-800 through DDR3-2133, with backward compatibility provided for DDR2-667 through DDR2-1066 devices. The PHYs are compiled into a hard macro that is optimized for specific foundry nodes. Each DDR3/2 PHY is constructed from the following libraries of components: the application specific SSTL I/O library, a single Address/Command macro block and multiple byte wide data macro blocks instantiated as many times as required to accommodate the memory channel width. A key component of the DesignWare DDR3/2 PHY is the extensive in system data training/calibration capability in order to maximize the overall timing budget and improve system reliability. The DesignWare DDR3/2 PHY contains calibration circuits for read data eye training (optimizes and maintains the optimal DQS offset into the center of the read data eye), write data eye training (optimizes and maintains the optimal DQS offset into the center of the write data eye), per-bit deskew training (minimizes bit to bit timing skew for reads and writes independently), DDR3 write leveling, and DDR3 read leveling.

 


Features : - Compatible with JEDEC standard DDR3, DDR3L and DDR2 SDRAMs and provides a DFI 2.1 interface to the memory controller
- Scalable architecture that supports the speed range from DDR2-667 up to DDR3-1600
- PHY Utility Bock (PUB) included as a soft IP utility that includes control features, such as write leveling and data eye training, and provides support for production testing of the DDR3/2 PHY
- Delivery of product as a hardened Mixed-Signal macrocell components allows precise control of timing critical delay and skew paths
- Low latency
- Per-bit deskew and embedded PLLs for high-speed operation and improved timing budget
- DFI 2.1 compliant interface to memory controller (1:1 or 1:2 options)
- Configurable external data bus widths between 8 and 64 bits in 8-bit increments plus ECC
- Permits operating with DDR3/2 SDRAMs using data widths narrower than the compiled data width
- Support for 1 to 4 memory ranks
Categories :
Tags : DDR3/2 PHY, DDR
Maturity : Available on request
Portability :
Type :
 Hard IP 
Foundry :
ST Microelectronics
Nodes :
28nm
Process :
FDSOI

Deliverables : - Verilog behavioral model
- Synopsys lib timing model
- LEF layout abstract views & GDSII layout cells
- Spice netlists for layout versus schematic (LVS) checks
- Detailed datasheets, implementation guide, IBIS models
CST Webinar Series



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