The S80251XC3 core implements a high-performance 16-bit microcontroller that executes the MCS®251 & MCS®51 instruction sets and includes a configurable range of features and integrated peripherals.
The core’s advanced architecture yields the fastest 8051/80251-compatible MCU available anywhere (at the time of its release). It employs separate instruction and data buses (Harvard architecture), branch prediction, branch target caches, and stacking/un-stacking speed-up features, and is able to execute some instructions in parallel. Dhrystone 2.1 tests show it to run 69.7 times faster than the original 8051 at the same frequency, without requiring an external arithmetic acceleration unit (such as an MDU). Representative 40nm LP ASIC implementations can run with clock frequencies in excess of 300MHz, offering an effective speed up of more than 1,500 times over early 8051 chips.
The S80251XC3 is also extremely energy efficient. Its small silicon footprint—the complete microcontroller (CPU and peripherals) can be under 35,000 gates in size—means there is very little power leakage. Its higher performance compared to other 8-bit or 16-bit MCUs allows clocking at lower frequencies. Users can also adjust the core’s energy consumption to match the processing workload via dynamic frequency scaling and independent control of the CPU and peripherals clocks.
The core has a rich set of optional features and pre-integrated peripherals, allowing function, performance, and area to be balanced for each specific application. Software development is facilitated by a single-wire or JTAG debugging interface that operates seamlessly within the ARM® Keil® C251 integrated development environment. Inexpensive debug pods and a complete reference design board package are available.
This 80251 core builds on CAST’s experience with hundreds of 8051 IP customers going back to 1997. Designed for easy reuse in ASICs, structured ASICs, or FPGAs, the core is strictly synchronous, with positive-edge clocking (except in the optional debug & SPI modules), synchronous or asynchronous reset, and no internal tri-states.