Cadence Design Systems, Inc. 
Part Number : IP4428C
Short Desc. : USB 2.0 PHY T40 LP
Overview :
The Cadence USB 2.0 PHY IP is a hard PHY macro for the TSMC 40LP process. Integrated I/O pads and ESD structures are available as an option. The Cadence USB 2.0 PHY IP supports the USB 2.0 specification at speeds up to 480Mbps (HS). It is designed to easily integrate with a Cadence IP Factory USB controller, or any third party controller with a UTMI-compliant interface. It also supports the USB On-The-Go supplement to provide USB host and USB device operation. This PHY IP is architected with CPF design flow and designed with low power considerations which make it a very mobile favorable design. It ’s especially good for IoT applications, e.g. wearing devices, whom usually powered by little battery and the long battery life hours is a very much desired product feature. Thanks to a wide design tolerance considered in this design, though this PHY is implemented and verified at TSMC 40LP proces s, it also offer the flexibility to be easily migrated to other 55nm/65nm, e.g. TSMC 55LP/65LP, 55LPe/65LPe (embedded flash process).
Features : - Compliant with USB 2.0, USB OTG, USB 1.1, and USB Battery Charging 1.2 Specifications
- Support for 9.6, 10, and 12MHz reference clock inputs, and their derivatives
- 8-bit or 16-bit UTMI interface for compatibility with existing designs
- Flexible built-in self-test (BIST) circuit and USB 2.0 test modes for electrical testing
- Reversible D+/D- lanes
- CDR and Elastic Buffer from serial stream on the USB
- High Speed (HS) mode up to 480Mbps, Full Speed (FS) up to 12Mbps, and Low Speed up to 1.5Mbps
- Supports Session Request Protocol (SRP) and Host Negotiation Protocol (HNP) for USB OTG
- VBUS charge, discharge, and detection for cost-sensitive, SRP-capable devices
- Extensive low-power features including Suspend mode
Categories :
Maturity : Pre-silicon
Portability :
Type :
 Hard IP 
Foundry :
Nodes :
Process :

Deliverables : - GDSII macros with abstract in LEF
- Verilog post layout netlist
- STA scripts for use at chip or standalone PHY levels
- SDF for back-annotated timing verification
- Verilog testbench with memory model, configuration files, and sample tests, Documentation
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