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 Cadence Design Systems, Inc. 
Part Number : IP4428C
Short Desc. : USB 2.0 PHY TSMC 40LP
Overview :

The Cadence USB 2.0 PHY IP is a hard PHY macro for the TSMC 40LP process. Integrated I/O pads and ESD structures are available as an option.
The Cadence USB 2.0 PHY IP supports the USB 2.0 specification at speeds up to 480Mbps (HS). It is designed to easily integrate with a Cadence IP Factory USB controller, or any third party controller with a UTMI-compliant interface. It also supports the USB On-The-Go supplement to provide USB host and USB device operation. This PHY IP is architected with CPF design flow and designed with low power considerations which make it a very mobile favorable design. It’s especially good for IoT applications, e.g. wearing devices, whom usually powered by little battery and the long battery life hours is a very much desired product feature.


Features : - Compliant with USB 2.0 Specification, backwards compatible to USB 1.1 Specification
- Compliant with USB Battery Charging 1.2 Specification
- Supports Host, Peripherals and OTG applications
- Supports Link Power Management (LPM)
- Comprehensive test features: Datapath loop back, Scan, Bypass
- Flexible built-in self-test (BIST) circuit and USB 2.0 test modes for electrical testing
- 8-bit 60MHz and 16-bit 30MHz parallel interfaces
Categories :
Maturity : Pre-silicon
Portability :
Type :
 Hard IP 
Foundry :
TSMC
Nodes :
40nm
Process :
LP

Deliverables : - Verilog behavioral modules for PHY module
- Verilog testbench with configuration files and sample tests
- Liberty timing model
- Layout abstract in LEF format
- GDSII with flat netlist for LVS
- LVS/DRC log files
- DFT views - ATPG netlist, CTL model, BSDL
- Documentation



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