Cadence Design Systems, Inc. 
Part Number : IP8240
Short Desc. : 16G Multi-protocol PHY USB3.1/PCIe Gen4/10G-KR/SATA/SGMII T16 FF+
Overview :
Multi-Link Multi-Protocol SerDes 16 Gbps silicon proven, on 14/16nm and below. This Cadence hard PHY is a solution for growth in data and compute demand for enterprise-level data communications, networking, and storage systems that is changing the architecture of datacenter devices. Our Serializer/Deserializer (SerDes) is designed for infrastructure and datacenter applications. features long reach equalization capability at very low active and standby power. Our SerDes offers very low latency for time critical application. The SerDes PHY IP is designed to simultaneously run PCIe, USB, Ethernet, SATA, and SGMII on a per lane basis. Multiple test features are embedded to this macro and easily accessible by the end-user. A user-friendly graphical interface called EyeSurfTM within this SerDes provides convenient access to real-time and non-destructive eye scope and bathtubs for monitoring the bit error rate (BER) and the link performance during live traffic. Our 16Gbps Multi-Link Multi-Protocol SerDes IP was made for growth in demand for enterprise-level data communications, networking and storage systems. Architecture of datacenter devices is changing the our SerDes PHY is a solution for a market that tolerates nothing but proven and predictable.
Features : - Silicon proven and fully characterized PHY
- High performance PHY for datacenter applications
- Low-latency, long reach and low power modes
- Wide range of protocols that support networking, storage and computing applications
- Multi-Link PHY: mix protocols within the same macro
- EyeSurf: non-destructive on-chip oscilloscope
- Extensive set of isolation, test modes and loop-backsincluding APB and JTAG
- Supports 16-bit, 20-bit, and 32-bit PIPE and non-PIPE interfaces
- Selectable serial pin polarity reversal for both transmit and receive paths
Categories :
Maturity : Silicon proven
Portability :
Type :
 Hard IP 
Foundry :
Nodes :
Process :

Deliverables : - Integration Views
- Soft PHY logic RTL wrapper, DFT-Verilog netlists with SS/FF, CTL, and BSDL
- High Volume Manufacturing (HVM) kit, IBIS-AMI kit
- Documentation
- Testboards available on demand
S2C: FPGA Base prototyping- Download white paper

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