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 Synopsys 
Part Number : dwc_lpddr4_multiphy_tsmc16ffpll
Short Desc. : LPDDR4 multiPHY - TSMC 16FF+LL
Overview :

The Synopsys DesignWare LPDDR4 multiPHY is a complete physical interface solution for many different kinds of JEDEC -standard mobile and PC/consumer SDRAMs. The LPDDR4 multiPHY is a complete physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system-in-package applications requiring highperformance LPDDR4/LPDDR3/DDR4/DDR3/DDR3L/DDR3U SDRAM interfaces operating at up to 3200 Mbps. The DesignWare LPDDR4 multiPHY is ideal for systems targeting multiple applications with varying performance requirements. For example, when used in a mobile application such as a smartphone, the system may prefer highperformance LPDDR4/3 mobile SDRAM support but when used in a larger form factor budget tablet application, the system may prefer DDR4 or DDR3 SDRAMs if they are lower cost. The DesignWare LPDDR4 multiPHY offers this flexibility.

Optimized for high performance, low latency, low area, low power, and ease of integration, the DesignWare LPDDR4 multiPHY is provided as a hard DDR PHY that is primarily delivered as GDSII and includes the application-specific I/Os. Supporting the GDSII-based PHY is the RTL-based PHY Utility Block (PUB) that includes PHY control features such as write leveling, data eye training, per-bit data deskew control, PVT compensation, and support for production testing of the LPDDR4 multiPHY. The LPDDR4 multiPHY includes a DFI 4.0 interface to the memory controller and can be combined with the DesignWare Enhanced Universal Memory Controller (uMCTL2) for a complete DDR interface solution.


Features : - Supports JEDEC standard LPDDR4, LPDDR3, DDR4, DDR3,DDR3L (1.35V DDR3), and DDR3U (1.25V DDR3) SDRAMs
- High-performance DDR PHY supporting data rates up to 3200 Mbps
- Per-bit deskew for both read and write data paths
- Per-bit deskew for address/ command bus when used with LPDDR4 and LPDDR3 SDRAMs
- Designed for rapid integration with Synopsys Enhanced Universal DDR Memory Controller (uMCTL2) for a complete DDR interface solution
- Includes application-specific DDR I/Os including programmable drive strength and on-die termination (ODT)
- DFI 4.0 compliant controller interface
Categories :
Tags : LPDDR4, multiPHY
Maturity : Available on request
Portability :
Type :
 Hard IP 
Foundry :
TSMC
Nodes :
20nm
Process :
PLL

Deliverables : - Executable .run installation file which includes GDSII, LEF files, LVS netlists, .lib/.db timing models, Verilog model, DRC/LVS log files, I/O IBIS Model, I/O HSPICE netlist, parameterized Verilog top-level PHY netlist files
- Sample Verification Environment, PHY data book, physical implementation guide, app notes, verification guide, installation guide, and implementation checklist
- PUB includes Verilog code, Synthesis/ STA constraints and scripts, sample verification environment, and data book
- DDR PHY compiler
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