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 Synopsys 
Part Number : dwc_usb2_picophy-tsmc_40lp25_otg
Short Desc. : USB 2.0 PHY, Picophy, TSMC 40 LP25
Overview :
The Synopsys DesignWare ® USB 2.0 picoPHY provides designers with a complete physical (PHY) layer IP solution, designed for low power mobile and consumer applications such as next-generation, feature-rich smartphones and mobile internet devices. The DesignWare USB 2.0 picoPHY IP delivers smaller die area (approximately 30 %) and lower leakage power compared to current USB 2.0 PHY IP products, for reduced silicon cost and longer battery life. Optimized for mobile and consumer electronic applications, the DesignWare USB 2.0 picoPHY implements the latest Battery Charger (version 1.1) and USB On-The- Go (OTG) version 2.0 specifications from the USB Implementer's Forum (USBIF). Architected for the industry's most advanced 1.8V process technologies, the USB 2.0 picoPHY is designed with features created to minimize effects due to variations in foundry process, device models, package and board parasitics.
Features : - Ported to over 50 different processes and configurations ranging from 180-nm to 28-nm
- USB nanoPHY and USB picoPHY offers a tunability feature that allows quick, post-silicon adjustments that occur due to process variations, or unexpected chip and board parasitic, without modifying the existing design
- USB 2.0 PHYs support Device, Host and OTG configurations
- Ported to over 50 different processes and configurations ranging from 180-nm to 28-nm
- USB nanoPHY and USB picoPHY offers a tunability feature that allows quick, post-silicon adjustments that occur due to process variations, or unexpected chip and board parasitic, without modifying the existing design
- USB 2.0 PHYs support Device, Host and OTG configurations
Categories :
Maturity : Available on request
Portability :
Type :
 Hard IP 
Foundry :
TSMC
Nodes :
40nm
Process :
LP

Deliverables : - GDSII layout and layer map files, LEF of pin size and locations, LVS netlist in HSPICE format and LVS report, DRC report
- Simulation model for digital blocks, Behavioral models for analog blocks
- Synopsys ’ PrimeTime STA results, Gate-level netlist and SDF timing file
- DesignWare USB 3.0 PHY Databook
- Digital test vectors (.wgl); scan test environment with Automatic Test Pattern Generation (ATPG) vectors
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: IoTPLL



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