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Cadence Design Systems, Inc.
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USB 3.0 xHCI Host Controller
USB 3.0 xHCI Host Controller IP offered by Cadence Design Systems Inc., operates in SuperSpeed (5Gbps), High-Speed (480Mbps), Full-Speed (12Mbps), and Low-Speed (1.5 Mbps) modes. The PHY interface complies with USB PHY Interface for PCI Express (PIPE) for USB 3.0, as well as USB 2.0 Transceiver Macrocell Interface (UTMI+) Specification.Cadence USB 3.0 xHCI Host Controller IP provides system-on-chip (SoC) designers with the most robust way to implement a USB interface in their applications. The USB IP is architected to quickly and easily integrate into any SoC as an integrated solution with any Cadence or third-party USB PHY IP. Host applications access the controller through the industry-standard ARM ® AMBA® AXI system bus with an optional PCI Express (PCIe) interface.
- Compliant with USB 3.0 and xHCI specifications
- SuperSpeed (5Gbps), High-Speed (480Mbps), Full-Speed (12Mbps), and Low Speed (1.5 Mbps) modes
- Configurable number of USB 2.0 and USB 3.0 ports
- Configurable number of supported devices
- Up to 15 IN and OUT endpoints per device
- PIPE interface for USB 3.0 and UTMI+ for USB 2.0
- AXI Master system bus interface with support for outstanding transactions
- SSIC Interface option for MIPI M-PHY
- Optional PCIe/M-PCIe system bus interface
- Support for all USB Power management modes
- Clean, readable, synthesizable Verilog RTL
- Synthesis and STA scripts
- Sanity check testbench with integrated BFM and monitors
- Documentation - Design specificataion, user guide
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