Part Number : dwc_shs_vl00x000vpnnstawc000s
Short Desc. : STAR Hierarchical System Wrapped Core Compiler Sync
Overview :

The DesignWare® STAR Hierarchical System is an automated hierarchical test solution for efficiently testing SoCs or designs using multiple IP/cores, including analog/mixed-signal IP, digital logic cores and interface IP. It significantly reduces test integration time by automatically creating a hierarchical IEEE 1500 network to access and control all IP/cores at the SoC level, and increases test quality of results (QoR), including optimizing test time and power through flexible test scheduling of IP and cores. It simplifies SoC test pattern creation by using the IEEE 1500 network to port IP or core-level patterns to the SoC-level, and allows silicon debug and diagnostics by enabling the IP debug test modes from the SoC level. The STAR Hierarchical System is compliant with the proposed IEEE standard P1687, which allows re-use of embedded test instruments for system-level debug. The system's highly automated design-for-test (DFT) implementation and hierarchical IP and core-level test enables engineering teams to cut their test integration time to a matter of days and bring their designs to market faster and with lower design and test costs.

Features : - Optimized hierarchical IEEE 1500 network reduces area and signal routes
- Efficient on-chip e-fuse programming for IP calibration/trimming
- ATE based and interactive access to IP debug test modes enables faster production ramp
- Hierarchical test accelerates SoC testing
- Automated test integration and validation of all IP/cores on SoC increases design and DFT productivity
- Flexible IP/core test scheduling optimizes test time and power . Automated porting of IP/core patterns to SoC-level enables reuse of test patterns
Categories :
Tags : Test & Repair IP for embedded memories
Maturity : Available on request
Portability :
Type : Hard
S2C: FPGA Base prototyping- Download white paper

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