Logicircuit, Inc 
Part Number : DO-254 AXI 7-Series
Short Desc. : DDRx (Limited) 1.00a
Overview :

The DO-254 AXI 7-Series DDRx (Limited) 1.00a uses the Xilinx®-7 Series FPGAs memory interface solutions to provide high-performance connections to DDR3 and DDR2 SDRAMs.  Xilinx®-7 Series FPGAs memory interface solutions core is a combined pre-engineered controller and physical layer (PHY) for interfacing 7 series FPGA user designs and AMBA® advanced extensible interface (AXI4) slave interfaces to DDR3 and DDR2 SDRAM devices.  In the Embedded Development Kit (EDK), this core is provided through the Xilinx® Platform Studio (XPS) as the DO-254 AXI 7-Series DDRx (Limited) 1.00a IP located in the DO-254 IP library with a static AXI4 to DDR3 or DDR2 SDRAM architecture.

Features : - Component support for interface widths up to 64 bits
- Single rank UDIMM and SODIMM support
- DDR3 (1.5 V) and DDR3L (1.35 V)
- 1, 2, and 4 Gb density device support
- 8-bank support
- x8 and x16 device support
- 8:1 DQ:DQS ratio support
- Configurable data bus widths (multiples of 8, up to 64 bits)
- 8-word burst support
- Support for 5 to 11 cycles of column-address strobe (CAS) latency (CL)
- On-die termination (ODT) support
- Support for 5 to 8 cycles of CAS write latency
- Write leveling support for DDR3 (fly-by routing topology required for DDR3 component designs)
- JEDEC-compliant DDR3 initialization support
- Source code written in Verilog
- 4:1 and 2:1 memory to FPGA logic interface clock ratio
- Internal VREF support
- Multicontroller support for up to eight controllers
Categories :
Portability :
Type : Soft
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: IoTPLL

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