Short Desc. : SH-4 32-bit RISC CPU Core Family
Overview :
The SH-4 is available in three groups, the integer SH4-400 group and SH4-500 group and with an integrated vector Floating Point Unit, the SH4-200 group. SH-4 cores deliver programmable multimedia solutions, for example the SH4-200 can execute in software an MPEG4 384Kbps, 15fps CIF decode in only 45MHz. Licensees can configure the size of the 2-way set associative instruction and data caches from 4KB to 64KB in all of the SH-4 family.
Features : - Dual issue (superscalar) CPU delivering 1.5DMIPS/MHz (Dhrystone 2.1)
- Optional 128-bit Vector Floating Point Unit (FPU)
- 16-bit encoded instruction set delivers class leading code density. The SH-4 instruction set is based on the popular SHcompact RISC instruction set and is the only licensable 32-bit CPU technology to offer an instruction set that is entirely 16-bit encoded.
- Efficient cache architecture: The SH-4 family has a 2-way set associative split cache architecture.
Categories :
Portability :
Type : Hard
S2C: FPGA Base prototyping- Download white paper

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