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 Altera 
Short Desc. : SPI Slave to Avalon Master Bridge
Overview :

 

1. Introduction

This user guide describes the IP cores provided by Altera that are included in the Quartus® II design software.

The IP cores are optimized for Altera® devices and can be easily implemented to reduce design and test time. You can use the IP parameter editor from Qsys or SOPC Builder to add the IP cores to your system, configure the cores, and specify their connectivity.

Tools Support

Qsys is a system-level integration tool which is included as part of the Quartus II software. Qsys leverages the easy-to-use interface of SOPC Builder and provides backward compatibility for easy migration of existing embedded systems.You can implement a design using the IP cores from the Qsys component library.

All the IP cores described in this user guide are supported by Qsys except for the following cores which are only supported by SOPC Builder.

  1. Common Flash Interface Controller Core
  2. SDRAM Controller Core (pin-sharing mode)
  3. DMA Controller Core

For more information on Qsys or SOPC Builder, refer to Volume 1: Design and Synthesis of the Quartus II Handbook or SOPC Builder User Guide.

Device Support

The IP cores described in this user guide support all Altera device families except the cores listed inTable 1–1.

Table 1–1. Device Support

IP Cores Device Support
Off-Chip Interfaces  
EPCS Serial Flash Controller Core All device families except HardCopy® series.
Cyclone III Remote Update Controller Core Only Cyclone III device.
MDIO Core Only Stratix® IV GX and Stratix IV GT devices.
On-Chip Interfaces  
On-Chip FIFO Memory Core All device families except HardCopy® series.
Clock Control  
Avalon ALTPLL Core All device families except Stratix V, Cyclone V, and Arria V device families.

Different device families support different I/O standards, which may affect the ability of the core to interface to certain components. For details about supported I/O types, refer to the device handbook for the target device family.

Obsolescence

The following IP cores are scheduled for product obsolescence and discontinued support:

  1. PCI Lite Core
  2. Mailbox Core

Altera recommends that you do not use these cores in new designs.

For more information about Altera’s current IP offering, refer to Altera’s Intellectual Property website.

Document Revision History

The following table shows the revision history for this document.

DateVersionChanges
June 2011 11.0

–  Removed System ID core from the list of cores which are only supported by SOPC Builder.
–  Converted the document to new frame template version 2.0 and made textual and style changes.

December 2010 10.1 Initial release.


 

Section I. Off-Chip Interface Peripherals

This section describes the interfaces to off-chip devices provided for SOPC Builder systems.

This section includes the following chapters:

  1. Chapter 2, SDRAM Controller Core
  2. Chapter 3, CompactFlash Core
  3. Chapter 4, Common Flash Interface Controller Core
  4. Chapter 5, EPCS Serial Flash Controller Core
  5. Chapter 6, JTAG UART Core
  6. Chapter 7, UART Core
  7. Chapter 8, SPI Core
  8. Chapter 9, Optrex 16207 LCD Controller Core
  9. Chapter 10, PIO Core
  10. Chapter 11, Avalon-ST Serial Peripheral Interface Core
  11. Chapter 12, PCI Lite Core
  12. Chapter 13, Cyclone III Remote Update Controller Core
  13. Chapter 14, MDIO Core

For information about the revision history for chapters in this section, refer to each individual chapter for that chapter ’s revision history.

 

2. SDRAM Controller Core

Core Overview

The SDRAM controller core with Avalon® interface provides an Avalon Memory-Mapped (Avalon-MM) interface to off-chip SDRAM. The SDRAM controller allows designers to create custom systems in an Altera® device that connect easily to SDRAM chips. The SDRAM controller supports standard SDRAM as described in the PC100 specification.

SDRAM is commonly used in cost-sensitive applications requiring large amounts of volatile memory. While SDRAM is relatively inexpensive, control logic is required to perform refresh operations, open-row management, and other delays and command sequences. The SDRAM controller connects to one or more SDRAM chips, and handles all SDRAM protocol requirements. Internal to the device, the core presents an Avalon-MM slave port that appears as linear memory (flat address space) to Avalon-MM master peripherals.

The core can access SDRAM subsystems with various data widths (8, 16, 32, or 64 bits), various memory sizes, and multiple chip selects. The Avalon-MM interface is latency-aware, allowing read transfers to be pipelined. The core can optionally share its address and data buses with other off-chip Avalon-MM tri-state devices. This feature is valuable in systems that have limited I/O pins, yet must connect to multiple memory chips in addition to SDRAM.

The SDRAM controller core with Avalon interface is SOPC Builder-ready and integrates easily into any SOPC Builder-generated system. This chapter contains the following sections:

  1. “Functional Description”
  2. “Hardware Simulation Considerations”
  3. “Software Programming Model”
  4. “Clock, PLL and Timing Considerations”

 

Functional Description

 

Figure 2–1 shows a block diagram of the SDRAM controller core connected to an external SDRAM chip.

Figure 2–1. SDRAM Controller with Avalon Interface Block Diagram

The following sections describe the components of the SDRAM controller core in detail. All options are specified at system generation time, and cannot be changed at runtime.

Avalon-MM Interface

The Avalon-MM slave port is the user-visible part of the SDRAM controller core. The slave port presents a flat, contiguous memory space as large as the SDRAM chip(s). When accessing the slave port, the details of the PC100 SDRAM protocol are entirely transparent. The Avalon-MM interface behaves as a simple memory interface. There are no memory-mapped configuration registers.

The Avalon-MM slave port supports peripheral-controlled wait states for read and write transfers. The slave port stalls the transfer until it can present valid data. The slave port also supports read transfers with variable latency, enabling high-bandwidth, pipelined read transfers. When a master peripheral reads sequential addresses from the slave port, the first data returns after an initial period of latency. Subsequent reads can produce new data every clock cycle. However, data is not guaranteed to return every clock cycle, because the SDRAM controller must pause periodically to refresh the SDRAM.

For details about Avalon-MM transfer types, refer to the Avalon Interface Specifications.

 

Off-Chip SDRAM Interface

The interface to the external SDRAM chip presents the signals defined by the PC100 standard. These signals must be connected externally to the SDRAM chip(s) through I/O pins on the Altera device.

Signal Timing and Electrical Characteristics

The timing and sequencing of signals depends on the configuration of the core. The hardware designer configures the core to match the SDRAM chip chosen for the system. See “Configuration” section.

for details. The electrical characteristics of the device pins depend on both the target device family and the assignments made in the Quartus® II software. Some device families support a wider range of electrical standards, and therefore are capable of interfacing with a greater variety of SDRAM chips. For details, refer to the device handbook for the target device family.

Synchronizing Clock and Data Signals

The clock for the SDRAM chip (SDRAM clock) must be driven at the same frequency as the clock for the Avalon-MM interface on the SDRAM controller (controller clock). As in all synchronous designs, you must ensure that address, data, and control signals at the SDRAM pins are stable when a clock edge arrives. As shown in Figure 2–1, you can use an on-chip phase-locked loop (PLL) to alleviate clock skew between the SDRAM controller core and the SDRAM chip. At lower clock speeds, the PLL might not be necessary. At higher clock rates, a PLL is necessary to ensure that the SDRAM clock toggles only when signals are stable on the pins. The PLL block is not part of the SDRAM controller core. If a PLL is necessary, you must instantiate it manually. You can instantiate the PLL core interface, which is an SOPC Builder component, or instantiate an ALTPLL megafunction outside the SOPC Builder system module.

If you use a PLL, you must tune the PLL to introduce a clock phase shift so that SDRAM clock edges arrive after synchronous signals have stabilized. See “Clock, PLL and Timing Considerations” for details.

f For more information about instantiating a PLL in your SOPC Builder system, refer to “PLL Cores” section. The Nios® II development tools provide example hardware designs that use the SDRAM controller core in conjunction with a PLL, which you can use as a reference for your custom designs. The Nios II development tools are available free for download from www.altera.com.

Clock Enable (CKE) Not Supported

The SDRAM controller does not support clock-disable modes. The SDRAM controller permanently asserts the CKE signal on the SDRAM.

Sharing Pins with Other Avalon-MM Tri-State Devices

If an Avalon-MM tri-state bridge is present in the SOPC Builder system, the SDRAM controller core can share pins with the existing tri-state bridge. In this case, the core’s addr, dq (data) and dqm (byte-enable) pins are shared with other devices connected to the Avalon-MM tri-state bridge. This feature conserves I/O pins, which is valuable in systems that have multiple external memory chips (for example, flash, SRAM, and SDRAM), but too few pins to dedicate to the SDRAM chip. See “Performance Considerations” section for details about how pin sharing affects performance.

Note: The SDRAM addresses must connect all address bits regardless of the size of the word so that the low-order address bits on the tri-state bridge align with the low-order address bits on the memory device. The Avalon-MM tristate address signal always presents a byte address. It is not possible to drop A0 of the tri-state bridge for memories when the smallest access size is 16 bits or A0-A1 of the tri-state bridge when the smallest access size is 32 bits.

Board Layout and Pinout Considerations

When making decisions about the board layout and device pinout, try to minimize the skew between the SDRAM signals. For example, when assigning the device pinout, group the SDRAM signals, including the SDRAM clock output, physically close together. Also, you can use the Fast Input Register and Fast Output Register logic options in the Quartus II software. These logic options place registers for the SDRAM signals in the I/O cells. Signals driven from registers in I/O cells have similar timing characteristics, such as tCO, tSU, and tH.

Performance Considerations

Under optimal conditions, the SDRAM controller core’s bandwidth approaches one word per clock cycle. However, because of the overhead associated with refreshing the SDRAM, it is impossible to reach one word per clock cycle. Other factors affect the core’s performance, as described in the following sections.

Open Row Management

SDRAM chips are arranged as multiple banks of memory, in which each bank is capable of independent open-row address management. The SDRAM controller core takes advantage of open-row management for a single bank. Continuous reads or writes within the same row and bank operate at rates approaching one word per clock. Applications that frequently access different destination banks require extra management cycles to open and close rows.

Sharing Data and Address Pins

When the controller shares pins with other tri-state devices, average access time usually increases and bandwidth decreases. When access to the tri-state bridge is granted to other devices, the SDRAM incurs overhead to open and close rows. Furthermore, the SDRAM controller has to wait several clock cycles before it is granted access again.

To maximize bandwidth, the SDRAM controller automatically maintains control of the tri-state bridge as long as back-to-back read or write transactions continue within the same row and bank.

Note: This behavior may degrade the average access time for other devices sharing the Avalon-MM tri-state bridge.

The SDRAM controller closes an open row whenever there is a break in back-to-back transactions, or whenever a refresh transaction is required. As a result:

  1. The controller cannot permanently block access to other devices sharing the tri-state bridge.
  2. The controller is guaranteed not to violate the SDRAM’s row open time limit.

Hardware Design and Target Device

The target device affects the maximum achievable clock frequency of a hardware design. Certain device families achieve higher fMAX performance than other families. Furthermore, within a device family, faster speed grades achieve higher performance. The SDRAM controller core can achieve 100 MHz in Altera’s high-performance device families, such as Stratix® series. However, the core might not achieve 100 MHz performance in all Altera device families.

The fMAX performance also depends on the SOPC Builder system design. The SDRAM controller clock can also drive other logic in the system module, which might affect the maximum achievable frequency. For the SDRAM controller core to achieve fMAX performance of 100 MHz, all components driven by the same clock must be designed for a 100 MHz clock rate, and timing analysis in the QuartusII software must verify that the overall hardware design is capable of 100 MHz operation.

 

Configuration

The SDRAM controller MegaWizard has two pages: Memory Profile and Timing. This section describes the options available on each page.

The Presets list offers several pre-defined SDRAM configurations as a convenience. If the SDRAM subsystem on the target board matches one of the preset configurations, you can configure the SDRAM controller core easily by selecting the appropriate preset value. The following preset configurations are defined:

  1. Micron MT8LSDT1664HG module
  2. Four SDR100 8 MByte × 16 chips
  3. Single Micron MT48LC2M32B2-7 chip
  4. Single Micron MT48LC4M32B2-7 chip
  5. Single NEC D4564163-A80 chip (64 MByte × 16)
  6. Single Alliance AS4LC1M16S1-10 chip
  7. Single Alliance AS4LC2M8S0-10 chip

Selecting a preset configuration automatically changes values on the Memory Profile and Timing tabs to match the specific configuration. Altering a configuration setting on any page changes the Preset value to custom.

 


Categories :
Portability :
 FPGA Technologis 
Altera :
Arria GX
Arria II GX
ARRIA II GZ
ARRIA V GX
ARRIA V GZ
Cyclone
Cyclone II
Cyclone III
CYCLONE III LS
CYCLONE IV GX
EP5C
HARDCOPY III
Stratix
Stratix II
Stratix II GX
STRATIX III E
STRATIX IV E
STRATIX IV GT
STRATIX IV GX
STRATIX V GX

Type : Hard
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