Short Desc. : SignalTap II Logic Analyzer
Overview :

13. Design Debugging Using the SignalTap II Logic Analyzer

Altera provides the SignalTap® II Logic Analyzer to help with the process of design debugging. This logic analyzer is a solution that allows you to examine the behavior of internal signals, without using extra I/O pins, while the design is running at full speed on an FPGA device.

The SignalTap II Logic Analyzer is scalable, easy to use, and is available as a stand-alone package or included with the Quartus® II software subscription. This logic analyzer helps debug an FPGA design by probing the state of the internal signals in the design without the use of external equipment. Defining custom trigger-condition logic provides greater accuracy and improves the ability to isolate problems. The SignalTap II Logic Analyzer does not require external probes or changes to the design files to capture the state of the internal nodes or I/O pins in the design. All captured signal data is conveniently stored in device memory until you are ready to read and analyze the data.

The topics in this chapter include:

  • “Design Flow Using the SignalTap II Logic Analyzer”
  • “SignalTap II Logic Analyzer Task Flow”
  • “Configure the SignalTap II Logic Analyzer”
  • “Define Triggers”
  • “Compile the Design”
  • “Program the Target Device or Devices”
  • “Run the SignalTap II Logic Analyzer”
  • “View, Analyze, and Use Captured Data”
  • “Other Features”
  • “Design Example: Using SignalTap II Logic Analyzers”
  • “Custom Triggering Flow Application Examples”
  • “SignalTap II Scripting Support”

The SignalTap II Logic Analyzer is a next-generation, system-level debugging tool that captures and displays real-time signal behavior in a system-on-a-programmablechip (SOPC) or any FPGA design. The SignalTap II Logic Analyzer supports the highest number of channels, largest sample depth, and fastest clock speeds of any logic analyzer in the programmable logic market. Figure 13–1: shows a block diagram of the components that make up the SignalTap II Logic Analyzer.

This chapter is intended for any designer who wants to debug an FPGA design during normal device operation without the need for external lab equipment. Because the SignalTap II Logic Analyzer is similar to traditional external logic analyzers, familiarity with external logic analyzer operations is helpful, but not necessary. To take advantage of faster compile times when making changes to the SignalTap II Logic Analyzer, knowledge of the Quartus II incremental compilation feature is helpful.

Note: For information about using the Quartus II incremental compilation feature, refer to the Quartus II Incremental Compilation for Hierarchical and Team-Based Design chapter in volume 1 of the Quartus II Handbook.

Hardware and Software Requirements

You need the following components to perform logic analysis with the SignalTap II Logic Analyzer:

  • Quartus II design software


        Quartus II Web Edition (with the TalkBack feature enabled)


        Signal Tap II Logic Analyzer standalone software, included in and requiring the Quartus II standalone Programmer software available from the Downloads page of the Altera website (www.altera.com)

  • Download/upload cable
  • Altera® development kit or your design board with JTAG connection to device under test

Note: The Quartus II software Web Edition does not support the SignalTap II Logic Analyzer with the incremental compilation feature.

The memory blocks of the device store captured data and transfers the data to the Quartus II software waveform display with a JTAG communication cable, such as EthernetBlaster or USB-BlasterTM.

Table 13–1 summarizes features and benefits of the SignalTap II Logic Analyzer.

Table 13–1. SignalTap II Logic Analyzer Features and Benefits (Part 1 of 2)

Feature Benefit
Multiple logic analyzers in a single device Captures data from multiple clock domains in a design at the same time.
Multiple logic analyzers in multiple devices in a single JTAG chain Simultaneously captures data from multiple devices in a JTAG chain.
Plug-In Support Easily specifies nodes, triggers, and signal mnemonics for IP, such as the Nios® II processor.
Up to 10 basic or advanced trigger conditions for each analyzer instance Enables sending more complex data capture commands to the logic analyzer, providing greater accuracy and problem isolation.
Power-Up Trigger Captures signal data for triggers that occur after device programming, but before manually starting the logic analyzer.
State-based Triggering Flow Enables you to organize your triggering conditions to precisely define what your logic analyzer captures.
Incremental compilation Modifies the SignalTap II Logic Analyzer monitored signals and triggers without performing a full compilation, saving time.
Flexible buffer acquisition modes The buffer acquisition control allows you to precisely control the data that is written into the acquisition buffer. Both segmented buffers and non-segmented buffers with storage qualification allow you to discard data samples that are not relevant to the debugging of your design.
MATLAB integration with included MEX function Collects the SignalTap II Logic Analyzer captured data into a MATLAB integer matrix.
Up to 2,048 channels per logic analyzer instance Samples many signals and wide bus structures.
Up to 128K samples in each device Captures a large sample set for each channel.

Table 13–1. SignalTap II Logic Analyzer Features and Benefits (Part 2 of 2)

Feature Benefit
Fast clock frequencies Synchronous sampling of data nodes using the same clock tree driving the logic under test.
Resource usage estimator Provides estimate of logic and memor y device resources used by SignalTap II Logic Analyzer configurations.
No additional cost The SignalTap II Logic Analyzer is included with a Quartus II subscription and with the Quartus II Web Edition (with TalkBack enabled).
Compatibility with other on-chip debugging utilities You can use the SignalTap II Logic Analyzer in tandem with any JTAG-based on-chip debugging tool, such as an In-System Memory Content editor, allowing you to change signal values in real-time while you are running an analysis with the SignalTap II Logic Analyzer.

Note: The Quartus II software offers a portfolio of on-chip debugging solutions. For an overview and comparison of all tools available in the In-System Verification Tool set, refer to Section IV. In-System Design Debugging

Design Flow Using the SignalTap II Logic Analyzer

Figure 13–2 shows a typical overall FPGA design flow for using the SignalTap II Logic Analyzer in your design. A SignalTap II file (.stp) is added to and enabled in your project, or a SignalTap II HDL function, created with the MegaWizard™ Plug-In Manager, is instantiated in your design. The figure shows the flow of operations from initially adding the SignalTap II Logic Analyzer to your design to final device configuration, testing, and debugging.

Categories :
Portability :
 FPGA Technologis 
Altera :
Arria GX
Arria II GX
Stratix II GX

Type : Hard
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: IoTPLL

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