Using the Serial FlashLoader with the Quartus II Software
Using the JTAG interface, the Altera® Serial FlashLoader (SFL) is the first in-system programming solution for Altera serial configuration devices. The SFL solution is available with the Quartus® II software version 4.1 SP1 and later. The SFL megafunction is available with the Quartus II software version 6.0 and later.
Because serial configuration devices do not support the JTAG interface, the conventional method to program them is via the active serial (AS) programming interface. With the AS programming interface, the configuration data used to program serial configuration devices is downloaded via programming hardware.
However, with the SFL you can program serial configuration devices in-system via the JTAG interface. To do so, use an FPGA as a bridge between the JTAG interface and the serial configuration device.
Table 1 lists the advantages and disadvantages of both methods.
Table 1. Advantages and Disadvantages
|Conventional: (AS Programming)
||Simple and fast
||Requires separate programming interface to configure FPGAs and program serial configuration devices.
|SFL solution: (JTAG Programming)
||Able to configure the FPGA and program serial configuration devices using the same JTAG interface
||Slow, because the SFL solution must configure the FPGA before programming serial configuration devices.
In version 9.0 and onwards of the Quartus II software, the enhanced mode of the SFL solution is introduced. This allows faster EPCS programming time with the following advantages:
- Enhanced SFL solution correctly interprets extra padding bits introduced by third programmer tool to ensure successful EPCS programming with SFL solution.
- Enhanced SFL allows conversion from JTAG Indirect Configuration (.jic) to Jam™ STAPL (.jam), JAM Byte-Code File (.jbc) or Serial Vector Format File (.svf) for multiple devices in JTAG chain in which only one device uses the SFL solution.
- Enhanced SFL allows conversion from .jic to .jam, .jbc, or .svf file for multiple devices in JTAG chain in which two or more devices uses the SFL solution.
Note: For more information on how to enable the enhanced SFL mode, refer to“Using the SFL Megafunction in the Quartus II Software” and “Programming Serial Configuration Devices with the Quartus II Programmer”.
The SFL supports FPGA families that configure using active serial configuration scheme. With the SFL megafunction, you can instantiate SFL image into user design. This feature allows you to perform SFL programming without resetting your design in the FPGA. The SFL solution provides more hardware programming options. For example, you can use the ByteBlaster™ II or USB-Blaster™ download cable, production tester, and other tools that have a JTAG interface.
Note: Whenever the term “serial configuration device or devices” is used in this document, it refers to Altera EPCS1, EPCS4, EPCS16, EPCS64, and EPCS128 devices.
This application note discusses the following topics:
“Programming Single and Multiple Serial Configuration Devices with the SFL Solution”
“Using the SFL Megafunction in the Quartus II Software” on page 7
“Generating .jic and .jam Programming Files in the Quartus II Software”
“Programming Serial Configuration Devices with the Quartus II Programmer”
Figure 1: shows both the conventional method of programming serial configuration devices as well as the in-system programming method using the SFL solution.
Figure 1. Conventional Versus the In-System Programming Method
Programming Single and Multiple Serial Configuration Devices with the SFL Solution
This section describes the three steps to program both single and multiple serial configuration devices with the SFL solution.
Note: To use the SFL solution, ensure that your board setup is in AS mode.
To program serial configuration devices using the SFL solution, perform the following steps (refer to Figure 2, Figure 3 and Figure 4):
1. To bridge the JTAG interface with the active serial memory interface (ASMI) block in the FPGA device, configure the SFL image into the FPGA. The previous design is replaced with the SFL image.
Note: You can bypass this step if the SFL image exists in the FPGA.
2. Program the serial configuration device or devices via the SFL image’s JTAGASMI bridge.
3. Reconfigure the FPGA with the new configuration data. This replaces the SFL image with the new design. To reconfigure the FPGA with the new configuration data, pull the nConfig pin low and release it to start configuration.
Figure 2 shows the SFL programming flow.
Figure 2. Serial Flash Loader Programming Flow
Figure 3 shows the programming of a single serial configuration device with the SFL solution.
Figure 3. Programming a Single Serial Configuration Device with the SFL Solution
More detailed information can be found here ...