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Short Desc. : SDI Video Interface
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SDI II MegaCore Function Features and Description

The Altera® SDI II MegaCore® function is Altera's next-generation SDI solution, which contains full features from the previous generation of SDI MegaCore function.

Altera recommends that you use SDI II MegaCore function for new designs.

The SDI II MegaCore function has the following new features:

  • VCXO removal feature
  • SMPTE 372 / 352 support for dual-link HD-SDI
  • RP168 support for synchronous video switching

Download the new SDI II MegaCore Function User Guide (PDF) now.

SDI MegaCore Function Features and Description

The Altera SDI MegaCore function implements a receiver, transmitter, or full-duplex serial digital interface (SDI) at standard definition (SD), high definition (HD), or 3 Gbps. The SDI MegaCore function also supports dual or triple-rate standards, which provide automatic receiver rate detection.

The Society of Motion Picture and Television Engineers (SMPTE) defined an SDI that video system designers widely use as an interconnect between equipment in video production facilities.

The SDI MegaCore function supports the following SDI data rates:

  • 270-megabits per second (Mbps) SD SDI, as defined by SMPTE259M-1997 10-Bit 4:2:2 Component Serial Digital Interface 1.485/1.4835 Gbps
  • HD SDI, as defined by SMPTE292M-1998 Bit-Serial Digital Interface for High-Definition Television Systems
  • SDI 3 Gbps, as defined by SMPTE425M-2006 3-Gbps Signal/Data Serial Interface–Source Image Format Mapping
  • Full support for dual-link SDI, as defined by SMPTE372M-Dual Link 1.5-Gbps Digital Interface for 1920 x 1080 and 2048 x 1080 Picture Formats
  • Dual standard that switches between 270 Mbps and 1.485 Gbps
  • Triple-rate SDI that switches between 270 Mbps, 1.485 Gbps, and 2.97 Gbps

Other SDI features include:

  • Support for multiple SDI standards (see Table 1)
  • Transmitter includes:
    • Cyclical redundancy check (CRC) encoding (HD only)
    • Line number (LN) insertion (HD only)
    • Word scrambling
  • Receiver includes:
    • CRC decoding (HD only)
    • LN extraction (HD only)
    • Framing and extraction of video timing signals
  • Word alignment and descrambling
  • Audio embed and extract
  • Clocked audio input and output
  • Intellectual property (IP) functional simulation models for use in VHDL and Verilog HDL simulators supported by Altera
  • IP Toolbench interface
  • Support for OpenCore Plus evaluation

Table 1 lists the SDI standards supported for various devices.

Table 1. SDI Standard Support
Device FamilySDI Standard
SDHD3 Gbps SDIHD-SDI Dual LinkTriple-Rate SDI
Stratix® V GX

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check

check

check

check

Stratix IV GX check check check check check
Stratix IV E check - - - -
Stratix III check - - - -
Stratix II GX check check check check check
Stratix II check - - - -
Stratix GX check check - check -
Cyclone® V GX

check

check

check

check

check

Cyclone IV GX check check check check check
Cyclone III check - - - -
Cyclone II check - - - -
Arria® V GX

check

check

check

check

check

Arria II GZ check check check - -
Arria II GX check check check check check
Arria GX check check check check check

OpenCore Plus Evaluation

Use the Altera OpenCore Plus Evaluation flow to test drive these MegaCore functions.

Performance

Typical expected performance and utilization figures for the MegaCore functions are provided in the following user guides:

I-Tested

Altera awards the I-Tested certification to MegaCore functions or Altera Megafunctions Partners Program (AMPPSM) IP cores that have been verified in an Altera FPGA on an evaluation board with the ASSPs, hardware components, or test equipment necessary to ensure interoperability according to the relevant protocols.


Categories :
Portability :
 FPGA Technologis 
Altera :
Arria GX
Arria II GX
ARRIA II GZ
ARRIA V GT
ARRIA V GX
Cyclone
Cyclone II
Cyclone III
CYCLONE III LS
CYCLONE IV GX
CYCLONE V GT
CYCLONE V GX
Stratix GX
Stratix II
Stratix II GX
STRATIX III E
STRATIX IV GT
STRATIX IV GX
STRATIX V GT
STRATIX V GX

Type : Hard
CST Webinar Series
S2C: FPGA Base prototyping- Download white paper



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