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 Altera 
Short Desc. : IP Compiler for PCI Express (Hard IP)
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OpenCore Plus Support
I-Test
Qsys Compliant



General Description

These popular PCIe MegaCore® functions (x1, x4, or x8 lane configurations) support all memory, I/O, configuration, and message transactions. The MegaCore functions have an optimized application interface to achieve maximum effective throughput. The MegaCore functions are also flexible and configurable, allowing customization for your specific needs. For example, the MegaCore functions support a configurable payload and a configurable retry buffer, and provide optional support for high-reliability features, such as ECRC and AER.

Altera has performed significant hardware testing of the PCIe x1, x4, and x8 IP MegaCore functions to ensure a reliable solution. These MegaCore functions have been tested internally with a variety of x86 motherboards, PCIe switch chips, and embedded microprocessors. Additionally, the hard IP MegaCore functions were tested at the PCI-SIG® compliance workshops and passed with high-quality results, including a 100 percent passing rate for the PCI-SIG gold tests.

Figure 1 shows a high-level block diagram of the PCIe hard IP block.

Figure 1. PCIe Hard IP Block

Additional Information and Resources

The following resources are available for you to easily adopt PCIe into your design:

Please contact an Altera sales representative to get a complete list of platforms tested for PCI-SIG compliance.

Resource Utilization and Performance

Estimated resource utilization and performance figures for this core are provided in the PCI Express Compiler User Guide (PDF).


Features :
Categories :
Portability :
 FPGA Technologis 
Altera :
Arria II GX
ARRIA II GZ
CYCLONE IV GX
HARDCOPY IV GX
STRATIX IV GT
STRATIX IV GX

Type : Hard
CST Webinar Series



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