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 Altera 
Short Desc. : Interlaken, 50G for 28nm devices
Overview :

 

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Qsys Compliant



Interlaken is a scalable protocol that enables chip-to-chip packet transfers at rates from 10 Gbps to 100 Gbps and beyond. Altera’s Interlaken intellectual property (IP) core continues to scale with today’s demand for more bandwidth and higher performance needs. Altera has been a part of the Interlaken Alliance since its inception in 2007 and continues to innovate new protocol features to provide customers with robust and easy-to-implement Interlaken IP solutions. Altera entered the market with 25G Interlaken IP cores and now offers 200G+ Interlaken IP cores.

Performance and Productivity

 

Performance Productivity
Parameter tuning enables bandwidth usage improvements as high as 35% 15% IP core timing margin accelerates full design timing closure
Consistent delivery of over 150 million packets / second on multiple customer platforms and across various vertical markets* OpenCore Plus feature allows you to test drive IP for free and without a license
Unique combination of hard & soft IP delivers high frequency user clocking performance (>250 MHz) and 30% reduced logic resourcing Fully integrated Interlaken IP includes MAC, PCS, and PMA layers for ease of FPGA IP integration

*Interlaken configuration specific

Accelerating Time to Market with Proven Altera and Cavium
Interlaken Connectivity

Altera's Interlaken IP core is ideal for multi-terabit routers and switches for access, carrier Ethernet, and data center applications that demand high IP configurability to optimize for system performance and interoperability. The Interlaken IP core also provides the necessary scalability for next-generation platforms. The combination of Altera’s Interlaken IP core in the Stratix® V FPGA with Cavium’s Octeon processors provides high throughput and bandwidth when workloads are at their peak.

To help simplify your design decision process and accelerate your time to market, Altera’s Interlaken IP core on the Stratix V FPGA has been validated with Cavium's Octeon multicore processors. This interoperability assures solution connectivity upfront when you develop with Altera and Cavium.

Read the press release.

Description

Figure 1 shows the interoperability setup between Altera's Interlaken IP core in the Stratix V FPGA and Cavium's Octeon multicore processor.

Figure 1. Altera and Cavium Interlaken Connectivity Setup

Table 1 summarizes the Altera and Cavium connectivity system.

Table 1. Altera and Cavium Connectivity System Overview

System OverviewDetails
Hardware

Altera: Stratix V FPGA development board with the Stratix V 5SGXEA7 FPGA
Cavium: EBB board with Octeon multicore processor

Interlaken configuration setup

8 lanes x 6.25 Gbps

Result Successfully passing traffic reliably using various packet sizes, logical channels, modes, and parameter settings

Altera's Interlaken IP Solution

The Interlaken IP core includes Altera’s technology-leading transceivers (PMA), physical coding sublayer (PCS), and MAC layers. The PCS and PMA layers are hardened within the Stratix V and Arria® V FPGAs, thereby saving customers 30 percent to 50 percent of FPGA logic resources. In addition to resource savings, the Interlaken IP has been through extensive simulation verification and has been proven to work on multiple internal and customer platforms. Altera's Interlaken IP solution has passed the Interlaken Alliance's device interoperability tests. Altera continues to set up interoperability activities with leading ASSP vendors for next-generation platforms.

Altera offers the MegaCore® function-based and customized Interlaken IP solutions. For more information, please contact your local Altera sales representative or email interlaken@altera.com.

Table 2 highlights the features and benefits of Altera's Interlaken IP.

Table 2. Features and Benefits

FeaturesBenefits
Data rate of up to 12.5 Gbps Maximizes platform flexibility to increase bandwidth and ensures scalability over time
Multi-lane configuration of up to 24 channels
Interleave (segment) mode and packet mode support Flexible data handling enables improvements to overall system performance
Dual segment support
Up to 256 logical channels
In-band and out-of-band flow control (calendar page options)

Resilient data transmission due to unexpected failures or glitches and reliable data integrity over multiple media

Retransmission
Tunable pre-emphasis and equalization settings

Figure 2. Typical Application Block Diagram

Figure 2. Typical Application Block Diagram

Altera's Interlaken IP core is supported on the following device families:

Related Links

Interlaken in the News


Categories :
Portability :
 FPGA Technologis 
Altera :
ARRIA V GX
ARRIA V GZ
STRATIX V GS
STRATIX V GT
STRATIX V GX

Type : Hard
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