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Short Desc. : In-System Sources & Probes
Overview :

16. Design Debugging Using In-System Sources and Probes

This chapter provides detailed instructions about how to use the In-System Sources and Probes Editor and Tcl scripting in the Quartus® II software to debug your design.

Traditional debugging techniques often involve using an external pattern generator to exercise the logic and a logic analyzer to study the output waveforms during run time. The SignalTap® II Logic Analyzer and SignalProbe allow you to read or “tap” internal logic signals during run time as a way to debug your logic design. You can make the debugging cycle more efficient when you can drive any internal signal manually within your design, which allows you to perform the following actions:

  • Force the occurrence of trigger conditions set up in the SignalTap II Logic Analyzer
  • Create simple test vectors to exercise your design without using external test equipment
  • Dynamically control run time control signals with the JTAG chain

The In-System Sources and Probes Editor in the Quartus II software extends the portfolio of verification tools, and allows you to easily control any internal signal and provides you with a completely dynamic debugging environment. Coupled with either the SignalTap II Logic Analyzer or SignalProbe, the In-System Sources and Probes Editor gives you a powerful debugging environment in which to generate stimuli and solicit responses from your logic design.

Note: The Virtual JTAG Megafunction and the In-System Memory Content Editor also give you the capability to drive virtual inputs into your design. The Quartus II software offers a variety of on-chip debugging tools. For an overview and comparison of all the tools available in the Quartus II software on-chip debugging tool suite, refer to Section IV. System Debugging Tools in volume 3 of the Quartus II Handbook.

Overview

This chapter includes the following topics:

  • Design Flow Using the In-System Sources and Probes Editor”
  • “Running the In-System Sources and Probes Editor”
  • “Tcl interface for the In-System Sources and Probes Editor"
  • “Design Example: Dynamic PLL Reconfiguration”

The In-System Sources and Probes Editor consists of the ALTSOURCE_PROBE megafunction and an interface to control the ALTSOURCE_PROBE megafunction instances during run time. Each ALTSOURCE_PROBE megafunction instance provides you with source output ports and probe input ports, where source ports drive selected signals and probe ports sample selected signals. When you compile your design, the ALTSOURCE_PROBE megafunction sets up a register chain to either drive or sample the selected nodes in your logic design. During run time, the In-System Sources and Probes Editor uses a JTAG connection to shift data to and from the ALTSOURCE_PROBE megafunction instances.Figure 16–1 shows a block diagram of the components that make up the In-System Sources and Probes Editor.

Figure 16–1. In-System Sources and Probes Editor Block Diagram



The ALTSOURCE_PROBE megafunction hides the detailed transactions between the JTAG controller and the registers instrumented in your design to give you a basic building block for stimulating and probing your design. Additionally, the In-System Sources and Probes Editor provides single-cycle samples and single-cycle writes to selected logic nodes. You can use this feature to input simple virtual stimuli and to capture the current value on instrumented nodes. Because the In-System Sources and Probes Editor gives you access to logic nodes in your design, you can toggle the inputs of low-level components during the debugging process. If used in conjunction with the SignalTap II Logic Analyzer, you can force trigger conditions to help isolate your problem and shorten your debugging process.

The In-System Sources and Probes Editor allows you to easily implement control signals in your design as virtual stimuli. This feature can be especially helpful for prototyping your design, such as in the following operations:

  • Creating virtual push buttons
  • Creating a virtual front panel to interface with your design
  • Emulating external sensor data
  • Monitoring and changing run time constants on the fly

The In-System Sources and Probes Editor supports Tcl commands that interface with all your ALTSOURCE_PROBE megafunction instances to increase the level of automation.

Hardware and Software Requirements

The following components are required to use the In-System Sources and Probes Editor:

  • Quartus II software

    or

  • Quartus II Web Edition (with the TalkBack feature turned on)
  • Download Cable (USB-BlasterTM download cable or ByteBlasterTM cable)
  • Altera® development kit or user design board with a JTAG connection to device under test
  • The In-System Sources and Probes Editor supports the following device families:
  • Arria® GX
  • Stratix® series
  • Cyclone® series
  • MAX® series

Design Flow Using the In-System Sources and Probes Editor

The In-System Sources and Probes Editor supports an RTL flow. Signals that you want to view in the In-System Sources and Probes editor are connected to an instance of the< ALTSOURCE_PROBE megafunction. After you compile the design, you can control each ALTSOURCE_PROBE instance via the In-System Sources and Probes Editor pane or via a Tcl interface. The complete design flow is shown in Figure 16–2.

Figure 16–2. FPGA Design Flow Using the In-System Sources and Probes Editor

Configuring the ALTSOURCE_PROBE Megafunction

To use the In-System Sources and Probes Editor in your design, you must first instantiate the ALTSOURCE_PROBE megafunction variation file. You can configure the ALTSOURCE_PROBE megafunction with the MegaWizard™ Plug-In Manager. Each source or probe port can be up to 256 bits. You can have up to 128 instances of the ALTSOURCE_PROBE megafunction in your design.

To configure the ALTSOURCE_PROBE megafunction, performing the following steps:

    1. On the Tools menu, click MegaWizard Plug-In Manager.
    2. Select Create a new custom megafunction variation.
    3. Click Next.
    4. On page 3 of the MegaWizard Plug-In Manager, make the following selections:

a. In the Installed Plug-Ins list, expand the JTAG-accessible Extensions folder and select In-System Sources and Probes.

Note: Verify that the currently selected device family matches the device you are targeting.

b. Select an output file type and enter the name of the ALTSOURCE_PROBE megafunction. You can choose AHDL (.tdf), VHDL (.vhd), or Verilog HDL (.v) as the output file type.

  1. Click Next.
  2. On page 3 of the MegaWizard Plug-In Manager, make the following selections:
    1. Under Do you want to specify an Instance Index?, turn on Yes.
    2. Specify the ‘Instance ID’ of this instance.
    3. Specify the width of the probe port. The width can be from 0 bit to 256 bits.
    4. Specify the width of the source port. The width can be from 0 bit to 256 bits.
  3. On page 3 of the MegaWizard Plug-In Manager, you can click Advanced Options and specify other options, including the following:
    1. What is the initial value of the source port, in hexadecimal?—Allows you to specify the initial value driven on the source port at run time.
    2. Write data to the source port synchronously to the source clock—Allows you to synchronize your source port write transactions with the clock domain of your choice.
    3. Create an enable signal for the registered source port—When turned on, creates a clock enable input for the synchronization registers. You can turn on this option only when the Write data to the source port synchronously to the source clock option is turned on.

Note: The In-System Sources and Probes Editor does not support simulation. You must remove the ALTSOURCE_PROBE megafunction instantiation before you create a simulation netlist.


Categories :
Portability :
 FPGA Technologis 
Altera :
Arria GX
Arria II GX
ARRIA V GX
CYCLONE III LS
CYCLONE IV GX
EP5C
Stratix II GX
STRATIX III E
STRATIX IV GT
STRATIX IV GX
STRATIX V GX

Type : Hard
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