I.9 BCH/BCH FEC IP Core
- Compliant with G.975.1 Annex 9
- 8.5dB net coding gain at 10-15 output BER
- 10G rates and variable rates in between
- Generic CPU interface for control and monitoring
- corrected bits
- corrected ones
- corrected zeros
- corrected codes
- uncorrectable codes
- Enables replacement of I.9 ASSPs
- Support for ASIC and FPGA implementation
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