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Short Desc. : G.709 RS(255,239) GFEC
Overview :

G.709 FEC IP Core

The Altera G.709 Forward Error Correction (G.709 FEC) IP core demonstrates the International Telecommunication Union-Telecommunication Standardization Sector (ITU-T) G.709 application of the Reed-Solomon (RS) algorithm in Optical Transport Network (OTN) data transmission. G.709 FEC implements the standardized RS (255, 239) code for transmission at 2.5 gigabits per second (Gbps)/Optical Channel Transport Unit (OTU)1, 10 Gbps/OTU2, 40 Gbps/OTU3, and 100 Gbps/OTU4.

Features

G.709 FEC includes the following features:

  • High-performance encoder and decoder for error detection and correction
    • Data transmission available for four OTN rates:
      • 2.5 Gbps/OTU1 with 16 bit datapath width
      • 10 Gbps/OTU2 with 64 bit datapath width
      • 40 Gbps/OTU3 with 256 bit datapath width
      • 100 Gbps/OTU4 with 640 bit datapath width
  • 7% overhead for Stratix® IV and Stratix V devices
  • Net electrical coding gain (NECG) of 6.5 dB
    • Error statistic monitoring, including the following types:
      • Corrected zeros and ones errors
      • Corrected errors and uncorrectable errors
      • 2.5 Gbps/OTU1, 10 Gbps/OTU2, 40 Gbps/OTU3, or 100 Gbps/OTU4 frame count

Architecture

Figure 1 illustrates the system architecture of the G.709 FEC IP core. Data from an incoming client is adapted to OTN before it is written to the OTN mapper. The data is encoded with redundant data at the FEC encoder before it is transmitted across the network. The redundant data is decoded at the FEC decoder and identified errors are corrected before the data is written to the OTN framer. The data is then adapted back to the original client.

Figure 1. G.709 FEC System Architecture



Device Family Support

Table 1 defines the device support levels for Altera IP cores.

Table 1. Altera IP Core Device Support Levels

FPGA Device Families HardCopy® Device Families
Preliminary support—The IP core is verified with preliminary timing models for this device family. The IP core meets all functional requirements, but might still be undergoing timing analysis for the device family. It can be used in production designs with caution. HardCopy Companion—The IP core is verified with preliminary timing models for the HardCopy companion device. The IP core meets all functional requirements, but might still be undergoing timing analysis for the HardCopy device family. It can be used in production designs with caution.
Final support—The IP core is verified with final timing models for this device family. The IP core meets all functional and timing requirements for the device family and can be used in production designs. HardCopy Compilation—The IP core is verified with final timing models for the HardCopy device family. The IP core meets all functional and timing requirements for the device family and can be used in production designs.

Table 2 lists the level of support for 2.5 Gbps G.709 FEC in each of the Altera device families.

Table 2. Device Family Support

Device FamilySupport
Stratix IV GX/GT Final
Stratix IV E Preliminary
Stratix V E/GX/GS/GT Preliminary
All other device families Not available

Table 3 lists the level of support for 10 Gbps, 40 Gbps, and 100 Gbps G.709 FEC in each of the Altera device families.

Table 3. Device Family Support

Device FamilySupport
Stratix IV GT Final
Stratix IV E/GX Preliminary
Stratix V E/GX/GS/GT Preliminary
All other device families Not available

IP Core Verification

Before releasing a version of the G.709 FEC IP core, Altera runs comprehensive regression tests to verify its quality and correctness.

Performance and Resource Utilization

The OTN frame consists of 4080 data bytes with 4 rows of information. The rate of data transmission determines the number of columns and datapath width for various speeds. G.709 FEC frame information is outlined in Table 4 .

Table 4. G.709 FEC Framing Information

 2.5 Gbps G.709 FEC10 Gbps G.709 FEC40 Gbps G.709 FEC100 Gbps G.709 FEC
Number of Columns 2040 510 126/127 51
Number of Rows 4 4 4 4
Datapath Width 2 bytes 8 bytes 32 bytes 80 bytes

Note to Table 4:

(1) The number of columns in the 40 Gbps OTN frame alternates between 126 and 127.

Figure 2 illustrates the input timing information for G.709 FEC at 100 Gbps. As shown, the IP core provides synchronous timing with the OTN column (i_col) and row (i_row) occurring with the positive edge of the system clock (sys_clk) and corresponding with the start of the OTN frame (denoted as F6F6... in the i_data port).

Figure 2. Example 100 Gbps G.709 FEC Input Timing Diagram

Stratix IV devices use combinational adaptive look-up tables (ALUTs) and logic registers. Table 5 shows the typical performance for 2.5 Gbps G.709 FEC on the Stratix IV GT (EP4S100G5H40I1(N)) device as reported by the Quartus® II software.

Table 5. Performance - 2.5 Gbps G.709 FEC on Stratix IV GT

OptionsALUTSLogic RegistersDecoder Memory (M9K)Memory (144K)fMAX (MHz)Net Electrical Gain (NECG)Latency
Encoder 297 2,178 0 blocks 0 blocks 383.73 6.5 dB 6.3 µs
Decoder 5,168 10,396 8 blocks 0 blocks 207.51

Table 6 shows the typical performance for 10 Gbps G.709 FEC on the Stratix IV GT (EP4S100G5H40I1(N)) device as reported by the Quartus II software.

Table 6. Performance - 10 Gbps G.709 FEC on Stratix IV GT

OptionsALUTSLogic RegistersDecoder Memory (M9K)Memory (144K)fMAX (MHz)Net Electrical Gain (NECG)Latency
Encoder 1,153 2,358 0 blocks 0 blocks 297.18 6.5 dB 6.3 µs
Decoder 7,872 12,206 8 blocks 0 blocks 226.55

Table 7 shows the typical performance for 40 Gbps G.709 FEC on the Stratix IV GT (EP4S100G5H40I1(N)) device as reported by the Quartus II software.

Table 7. Performance - 40 Gbps G.709 FEC on Stratix IV GT

OptionsALUTSLogic RegistersDecoder Memory (M9K)Memory (144K)fMAX (MHz)Net Electrical Gain (NECG)Latency
Encoder 3,500 3,127 0 blocks 0 blocks 212.53 6.5 dB 6 µs
Decoder 25,000 23,155 17 blocks 0 blocks 204.92

Table 8 shows the typical performance for 100 Gbps G.709 FEC on the Stratix IV GT (EP4S100G5H40I1(N)) device as reported by the Quartus II software.

Table 8. Performance - 100 Gbps G.709 FEC on Stratix IV GT

OptionsALUTSLogic RegistersDecoder Memory (M9K)Memory (144K)fMAX (MHz)Net Electrical Gain (NECG)Latency
Encoder 8,500 5,556 0 blocks 0 blocks 242.51 6.5 dB < 1 µs
Decoder 44,000 44,415 22 blocks 0 blocks 220.9

The nominal latency for the 100 Gbps G.709 FEC encoder is 5 clock cycles and the decoder is 161 clock cycles. The nominal latency is produced by continuously asserting the i_data_en port on the encoder and decoder; this allows the core to run at the full rate.

Port Listing

Table 9: lists the encoder input and output ports for connecting to the 2.5 Gbps, 10 Gbps, and 40 Gbps G.709 FEC IP cores.

Table 9. Encoder I/O Port Listing for 2.5 Gbps, 10 Gbps, and 40 Gbps G.709 FECs

I/OPort2.5 Gbps Port Width (Bits)10 Gbps Port Width (Bits)40 Gbps Port Width (Bits)Description
Input sys_clk 1 1 1 Clock port.
Input i_enable_n 1 1 1 Input enable encoder and decoder port. This is a synchronous signal and is active low.
Input i_row 2 2 2 Input OTN frame row port. This is a synchronous signal.
Input i_col 11 9 7 Input OTN frame column port. This is a synchronous signal.
Input i_data 16 64 256 Input data port.
Output o_row 2 2 2 Output OTN frame row port. This is a synchronous signal.
Output o_col 11 9 7 Output OTN frame column port. This is a synchronous signal.
Output o_data 16 64 256 Output data port.

Categories :
Portability :
 FPGA Technologis 
Altera :
STRATIX IV GT
STRATIX V GT
STRATIX V GX

Type : Hard
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