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Short Desc. : FIR Compiler II
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OpenCore Plus Support

Altera recommends the use of FIR Compiler II MegaCore® function for new designs. The FIR Compiler II MegaCore function provides significantly lower FPGA resource usage and increased performance than the original FIR Compiler for most FIR filter implementations. The original FIR Compiler MegaCore function will continue to be supported for existing designs.

Features and Description

The Altera® FIR Compiler II MegaCore function generates finite impulse response (FIR) filters customized for Altera devices. You can use the IP Toolbench interface to implement a variety of filter architectures, including fully parallel, serial, or multibit serial distributed arithmetic and multicycle fixed/variable filters. The FIR Compiler II MegaCore function also includes a coefficient generator.

The FIR Compiler II MegaCore function speeds your design cycle by:

  • Providing a fully integrated FIR filter development environment
  • Generating the coefficients needed to design custom FIR filters
  • Generating bit-accurate and clock-cycle-accurate FIR filter models in Verilog HDL, VHDL, and MATLAB
  • Automatically generating the code required for the Quartus® II software to synthesize high-speed, area-efficient FIR filters of various architectures
  • Creating Quartus II test vectors to test the FIR filter's impulse response
  • Generating a VHDL testbench for all architectures

The FIR Compiler II MegaCore function generated by this compiler also:

  • Supports a variety of distributed arithmetic and multiplier-based filter architectures up to 2,047 taps
  • Generates MATLAB simulation models and testbench
  • Generates a VHDL testbench for all architectures
  • Is highly optimized for Altera device architectures
  • Provides precision control of chip resource utilization
    • Utilizes logic cells, M512, M4K, M-RAM, MLAB, M9K, or M144K blocks for data storage
    • Utilizes logic cells, M512, M4K, MLAB, or M9K blocks for coefficient storage

IP Evaluation

Use the Altera OpenCore Plus Evaluation flow to test drive this core.

Performance and Resource Utilization

Typical expected performance and utilization figures for this core are provided in the FIR Compiler II MegaCore Function User Guide (PDF).


Categories :
Portability :
 FPGA Technologis 
Altera :
Arria GX
Arria II GX
ARRIA II GZ
ARRIA V GT
ARRIA V GX
Cyclone
Cyclone II
Cyclone III
CYCLONE III LS
CYCLONE IV GX
CYCLONE V E
CYCLONE V GT
CYCLONE V GX
CYCLONE V SE
CYCLONE V ST
CYCLONE V SX
HardCopy II
HARDCOPY III
HARDCOPY IV E
HARDCOPY IV GX
Stratix
Stratix GX
Stratix II
Stratix II GX
STRATIX III E
STRATIX IV GT
STRATIX IV GX
STRATIX V E
STRATIX V GT
STRATIX V GX

Type : Hard
S2C: FPGA Base prototyping- Download white paper



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