Short Desc. : DisplayPort Video Interface (up to 5.4Gbps)
Overview :
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OpenCore Plus Support
Qsys Compliant

DisplayPort is an audio or video high-speed serial interface standard supported by industry leaders in broadcast, consumer, medical, and military applications. This protocol replaces digital video interface (DVI) and high-definition multimedia interface (HDMI) outside and LVDS inside the application box for higher resolution (> 4Kx2K), higher frame rate and color bit depth display.

The Altera® DisplayPort MegaCore® function implements a receiver and transmitter at raw bit rate of 1.62, 2.7, or 5.4 Gbps per lane with support to have 1, 2, or 4 differential data pairs (lanes) in a Main Link. Data is 8b/10b encoded where each 8 bits of information is encoded with a 10 bit symbol. So the effective data rates after decoding are 1.296, 2.16, and 4.32 Gbps per lane (or 80% of the total) and support DisplayPort v1.2 specification.

Stratix® V, Arria® V, and Cyclone® V FPGAs provide fully integrate and silicon-proven DisplayPort design examples and can be found in the MegaCore function. The IP core also includes simulation design examples for various device families. These examples provide a starting point for you to understand the Altera video design methodology quickly, enabling you to build full video processing systems on an FPGA.

Figure 1. DisplayPort Design Example

Figure 1. DisplayPort Design Example

OpenCore Plus Evaluation

Use the Altera OpenCore Plus Evaluation flow to test drive this MegaCore function.


Typical expected performance and utilization figures for this MegaCore function are provided in the DisplayPort MegaCore Function User Guide (PDF).


Altera awards the I-Tested certification to MegaCore functions or Altera Megafunctions Partners Program (AMPPSM) IP cores that have been verified in an Altera FPGA on an evaluation board with the ASSPs, hardware components, or test equipment necessary to ensure interoperability according to the relevant protocols.

Features :
  • Conforms to the Video Electronics Standards Association (VESA) specification version 1.2a
  • Limited support for eDP v1.3 standard with fast link training feature
  • Scalable main data link: 1, 2 or 4 lane operation with 1.62 / 2.7 / 5.4 Gbps per lane with an embedded clock
  • Deep color support from 16, 18, 20, 24, 30, 32, 36 or 48 bits per pixel (bpp) in both RGB / YCrCb modes
  • Source
    • Embedded controller AUX channel operation
    • Supports audio and video streams
  • Sink
    • Finite state machine (FSM) and embedded controller AUX channel operation
  • Auxiliary channel for 2-way communication (link and device management)
  • Hot plug detect (HPD)
  • AC coupling and low EMI
  • Avalon┬« Memory-Mapped (Avalon-MM) interfaces for run-time control input and
    connections to external memory blocks
  • Easy-to-use parameter editor for parameterization and hardware generation
  • IEEE-encrypted simulation models for use in Altera-supported VHDL and
    Verilog HDL simulators
  • Support for OpenCore┬« Plus evaluation
  • Qsys ready

Categories :
Portability :
 FPGA Technologis 
Altera :

Type : Hard
CST: Webinars Begin on February 9
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: IoTPLL

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