Figure 1 shows a high-level block diagram of the Cyclone® V Hard IP for PCI Express block.
Figure 1 Cyclone V Hard IP for PCI Express Block Diagram
Cyclone V Hard IP for PCI Express: Cyclone V devices feature up to two implementations of hard PCIe circuitry. The hard IP can be configured as Gen1 x1 or x4 and Gen2 x1. The hard IP has an optimized application interface to help you achieve maximum effective throughput. You can parameterize the PCIe interface for various customizations to meet your specific needs. For example, there is support for a configurable payload and a configurable retry buffer, and optional support for high-reliability features, such as ECRC and AER. The Cyclone V hard IP also provides multifunction support to enable multiple endpoints to appear as a single endpoint to the root port.
Additional Information and Resources
The following resources are available for you to easily adopt PCIe into your design:
- Complete and detailed documentation of the IP core
- Complete description of the FPGA capabilities
- Free online training
- Complementary partner solution
Please contact an Altera® sales representative to get a complete list of platforms tested for PCI-SIG® compliance.
Resource Utilization and Performance
Estimated resource utilization and performance figures for this core are provided in the Cyclone V Hard IP For PCI Express User Guide (PDF)