Short Desc. : Avalon MM Master BFM w/Avalon ST API Wrapper
Overview :

Section I. Introduction to Avalon Verification IP Suite

The Avalon® Verification IP Suite provides bus functional models (BFMs) to simulate the behavior of and to facilitate the verification of IP that includes the following interfaces and components:

  • Avalon Memory-Mapped (Avalon-MM) master and slave interfaces
  • Avalon Streaming (Avalon-ST) source and sink interfaces
  • Conduit interfaces and Avalon Tri-State conduit (Avalon-TC) interfaces
  • Clock source and reset source
  • Interrupt source and sink
  • Custom instruction master and slave
  • External memory

This suite also provides the following monitors to verify the respective Avalon protocols:

  • Avalon-MM monitor
  • Avalon-ST monitor

Advantages of Using BFMs and Monitors

Using the Altera-provided BFMs and monitors has the following advantages:

  • It accelerates the verification process by providing key components of the verification testbench.
  • It provides Avalon BFM components that implement the standard Avalon-MM and Avalon-ST protocols, serving as a reference for those protocols.
  • For SystemVerilog users, it provides a platform that you can use to implement constraint-driven randomized tests, including traffic scenario drivers, scoreboard and coverage facilities, and assertion checkers.

BFM Implementation

The Avalon Verification IP Suite BFMs (excluding the Clock Source and Reset Source BFMs that are written in VHDL) are implemented in SystemVerilog. The BFM components use primarily Verilog HDL with a few basic SystemVerilog constructs that are supported by ModelSim®-Altera Edition (AE).

The Quartus II software version 13.0 and higher extends VHDL BFM support in Qsys. The VHDL BFMs wrap the SystemVerilog implementation and additional logic to support VDHL.

Table 1–1 for a summary of BFM language support.

Table 1–1. BFM Language Support

The VHDL BFM has four parts (see Figure 1–1):

  • SystemVerilog BFM—Contains the BFM implementation and behavioral model, and the SystemVerilog API. The SystemVerilog code is IEEE encrypted for use in single-language simulators.
  • VHDL package—Provides the VHDL API used to control the BFM and interface with your test program. The package contains VHDL procedures and events.
  • API handler logic—SystemVerilog logic block that translates your test program’s VHDL API calls to SystemVerilog API calls. The SystemVerilog code is IEEE encrypted for use in single-language simulators.
  • API communication interface—Bridges the VHDL API to the API handler logic.

Figure 1–1. VHDL Component BFM

The monitor components use the SystemVerilog Assertion (SVA) language and are supported only by simulators that support SVA, including: Modelsim-Altera Starter Edition (ASE), Synopsys VCS, and Mentor Graphics® Questa.

Application Programming Interface

Altera provides you with a set of application programming interface (API) for each Avalon Verification IP Suite BFM that you can use to construct, instantiate, control, and query signals in all BFM components. Your test programs must use only these public access methods and events to communicate with each BFM.

Note: While you can use methods other than the API, Altera does not guarantee continued support or backwards compatibility of custom methods.

Application Example of BFMs

Figure 1–1 shows the top-level blocks in a typical testbench to verify components with Avalon-MM and Avalon-ST interfaces.

Figure 1–1. Avalon Verification IP Suite Testbench

Figure 1–1 illustrates, it is possible to write a testbench using a traditional Verilog HDL implementation or using SystemVerilog with VMM. For illustration purposes, Figure 1–1 shows an Avalon-MM design under test (DUT) that includes both Avalon-MM master and slave interfaces, and an Avalon-ST DUT that includes both source and sink interfaces, although typical components might include a single Avalon interface.

When verifying a component with Avalon-MM or Avalon-ST interfaces, a monitor is inserted between the master or source BFM and the slave or sink interface of the DUT. A second monitor can be interposed between the slave or sink BFM and the master or source interface of the DUT. The monitors do not have to be placed between a BFM component and another component. They can be inserted anywhere in the system to provide protocol assertion checking and functional coverage reporting.

The test program drives the stimulus to the DUTs and determines whether the DUTs’ behavior is correct, by analyzing the responses. The BFMs translate the test program stimuli, creating the signalling for the Avalon-MM and Avalon-ST protocols. The monitors verify Avalon protocol compliance and provide test coverage reports.

More detailed information can be found here ...

Categories :
Portability :
 FPGA Technologis 
Altera :
Arria GX
Arria II GX
Cyclone II
Cyclone III
Stratix II
Stratix II GX

Type : Hard
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers

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