This topic describes the implementation and structure of the Qsys interconnect for memory-mapped interfaces. The content pertainsto bothAvalon andAXI memory-mapped interfaces, unless noted otherwise.
Memory-mapped transactions between masters and slaves are encapsulated in packets and transmitted on a network that carries the packets between masters and slaves. The command network transports read and write command packets from master interfaces to slave interfaces. The response network transports response packets from slave interfaces to master interfaces.
For each component interface, Qsys interconnect manages memory-mapped transfers, interacting with signals on the connected component. Master and slave interfaces can contain different signals and the interconnect processes any adaptation necessary between them. In the path between master and slaves, the Qsys interconnect might introduce registers for timing synchronization, finite state machines for event sequencing, or nothing at all, depending on the services required by the specific interfaces.
Qsys interconnect supports the following implementation scenarios:
- Any number of components with master and slave interfaces. The master-to-slave relationship can be one-to-one, one-to-many, many-to-one, or many-to-many.
- Master and slaves of different data widths.
- Master and slaves operating in different clock domains.
- IP Components with different interface properties and signals. Qsys adapts the component interfaces so that interfaces with the following differences can be connected:
- Avalon and AXI interfaces that use active-high and active-low signalling. AXI signals are active high, except for the reset signal.
- Interfaces with different burst characteristics.
- Interfaces with different latencies.
- Interfaces with different data widths.
- Interfaces with different port signatures.
Note: AXI3/4 to AXI3/4 interface connections declare a fixed set of signals with variable latency, so there is no need for adapting between active-high/low signalling, burst characteristics, different latencies, or port signatures. Some adaptation is necessary when going to or from Avalon interfaces.
Figure 8-1 illustrates the Qsys interconnect for an Avalon-MM system with multiple masters. In this example, there are two components mastering the system, a processor and a DMA controller, each with two master interfaces. The masters connect through the Qsys interconnect to several slaves in the Qsys system. The blue blocks represent interconnect components. The dark grey boxes indicate items outside of the Qsys system and the Quartus II software design, and show how component interfaces can be exported and connected to external devices.
Packet Format for Memory-Mapped Interfaces
The Qsys packet format supports Avalon, AXI, and APB transactions. Memory-mapped transactions between masters and slaves are encapsulated in Qsys packets. For Avalon systems without AXI or APB interfaces, some fields are ignored or removed.
Qsys Packet Format
The fields of the Qsys packet format are variable length to minimize the resources used. However, if the majority of components in a design have a single data width, for example 32-bits, and a single component has a data width of 64-bits, Qsys inserts a width adapter to accommodate 64-bit transfers.
Table 8-1 describes the fields of the Qsys packet that encapsulate the memory-mapped master commands and memory-mapped slave responses.
More detailed information can be found here ...