Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction
This user guide describes the features and behavior of the ALTPLL_RECONFIG megafunction that you can configure through the parameter editor in the Quartus® II software.
Note: This user guide assumes that you are familiar with megafunctions and how to create them. If you are unfamiliar with Altera megafunctions or the parameter editor, refer to the Introduction to Megafunctions User Guide.
Phase-locked loops (PLLs) use divide counters and voltage-controlled oscillator (VCO) phase taps to perform frequency synthesis and phase shifts. In enhanced and fast PLLs, you can reconfigure the counter settings as well as phase shift the PLL output clock in real time. You can also change the charge-pump and loop-filter components, which dynamically affect the PLL bandwidth. The ALTPLL_RECONFIG megafunction implements reconfiguration logic to facilitate dynamic real-time reconfiguration of PLLs in Altera devices. You can use the megafunction to update the output clock frequency, PLL bandwidth, and phase shifts in real time, without reconfiguring the entire FPGA.
The ALTPLL_RECONFIG megafunction offers the following additional features to the ALTPLL megafunction:
- Reconfiguration of pre-scale counter (N) parameters.
- Reconfiguration of feedback counter (M) parameters.
- Reconfiguration of post-scale output counter (C) parameters.
- Reconfiguration of delay element or phase shift of each counter. For Stratix® III, Stratix IV, Cyclone® III, Cyclone IV, HardCopy® III, HardCopy IV, and Arria® II GX devices, use the ALTPLL megafunction to access this feature.
- Dynamic adjustment of the charge-pump current and loop-filter components to facilitate dynamic reconfiguration of the PLL bandwidth. This feature is available only in Arria GX, HardCopy II, Stratix II, Stratix II GX, Stratix III, and Stratix IV devices.
- Reconfiguration from multiple configuration files using external read-only memory (ROM) in user mode. This feature is available only in Stratix III, Stratix IV, Cyclone III, Cyclone IV, and Arria II GX devices. The ALTPLL_RECONFIG supports reconfiguration from Memory Initialization File (.mif) and Hexadecimal File (.hex).
Note: For more details about these features, refer to the Clock Networks and PLLs chapter of the respective device handbook.
Use the ALTPLL_RECONFIG megafunction in designs that must support dynamic changes in the frequency and phase shift of clocks and other frequency signals. The megafunction is also useful in prototyping environments because it allows you to sweep PLL output frequencies and dynamically adjust the output clock phase. For example, a system generating test patterns is required to generate and transmit patterns at 50 or 100 MHz, depending on the device under test. Reconfiguring the PLL components in real-time allows you to switch between two such output frequencies within a few microseconds. You can also adjust the clock-to-output (tCO) delays in real-time by changing the output clock phase shift. This approach eliminates the need to regenerate a configuration file with the new PLL settings.
Reconfigurable PLLs are very useful in DDR 2 and DDR 3 interfaces to implement the dynamic data path (via the ALTMEMPHY megafunction). The PLL is needed to drive the DLL used in the dynamic external memory interface operation. This operation requires dynamic phase-shifting.
Note: For more information about dynamic phase-shifting in DDR 2 and DDR 3 interfaces, refer to the ALTMEMPHY Megafunction User Guide
In addition, you can dynamically configure Stratix III, Stratix IV, Cyclone III, Cyclone IV, and Arria II GX PLLs by using multiple configuration files stored on the external ROM.
Device Family Support
The megafunction supports the Stratix series (excluding Stratix V), HardCopy series, Arria GX series, and Cyclone series devices.
Resource Utilization and Performance
For details about the resource usage and performance of the ALTPLL_RECONFIG megafunction in various devices, refer to the compilation reports in the Quartus II software.
To view the compilation reports for the ALTPLL_RECONFIG megafunction in the Quartus II software, follow these steps:
- On the Processing menu, click Start Compilation to run a full compilation.
- After compiling the design, on the Processing menu, click Compilation Report.
- In the Table of Contents browser, expand the Fitter folder by clicking the “+” icon.
- Under Fitter, expand Resource section, and select Resource Usage Summary to view the resource usage information.
- Under Fitter, expand Resource section, and select Resource Utilization by Entity to view the resource utilization information.
Altera recommends that you configure the megafunction using the MegaWizard™ Plug-In Manager. This section describes the parameters in the ALTPLL_RECONFIG parameter editor.
Expert users may choose to instantiate and configure the megafunction using the clear box generator.
Table1: lists the parameter settings for the ALTPLL_RECONFIG megafunction.
You can open a .mif in a text editor to make use of the comments embedded within the file. These comments show you the scan chain values and positions based on your design parameterization (see Figure 1). If you open a .mif in the Quartus II software, you can regenerate the .mif in the ALTPLL parameter editor to restore the comments.
Figure 1. MIF file
Note: For more information about implementing PLL reconfiguration in the supported Stratix series, refer to AN 282: Implementing PLL Reconfiguration in Stratix & Stratix GX Devices, AN 367: Implementing PLL Reconfiguration in Stratix II Devices and AN 454: Implementing PLL Reconfiguration in Stratix III Devices.
Checking Design Violations With the Design Assistant
The Design Assistant is a design rule checking tool that allows you to check for design issues early in the design flow. When you run the Design Assistant in the Quartus II software for the ALTPLL_RECONFIG megafunction, you might receive the warning message shown in Figure 2.
Figure 2. Warning Message in Design Assistant
This message appears because there is a combinational logic in the megafunction that connects the synchronous signal to the asynchronous external reset signal. To fix the issue, you must synchronize the external reset signal outside the megafunction.
To synchronize the external reset signal, use the sample Verilog HDL code shown in Example 1 .In the example, the input of sync_reset_dffe1 is connected to the external reset pin, and the output of sync_reset_dffe2 is connected to the reset input port of the ALTPLL_RECONFIG megafunction.
Example 1. Code to Synchronize External Reset Signal
module synch_reg (reset, reconfig_clk, sync_reset_dffe2);
input reset, reconfig_clk;
reg sync_reset_dffe1, sync_reset_dffe2;
always @(posedge reconfig_clk)
sync_reset_dffe1 = reset;
always @(posedge reconfig_clk)
sync_reset_dffe2 = sync_reset_dffe1;
More detailed information can be found here ...