Altera offers the 40 Gbps Ethernet (40GbE) and 100 Gbps Ethernet (100GbE) MegaCore® function intellectual property (IP) cores for building systems with very high throughput-rate standard Ethernet connections. These IEEE 802.3ba-2010 40 Gbps and 100 Gbps Ethernet standard compliant media access control (MAC) and PHY (PCS+PMA) IP cores enable an Altera® device to interface to another device or to an optical transceiver module and, in turn, to 40GbE and 100GbE networks.
Figure 1 illustrates an example of Altera 40GbE or 100GbE MAC with a XLAUI, CAUI or CAUI-4 interface in an Altera device. 40GbE and 100GbE are two different IP cores.
Figure 1. 40GbE or 100GbE MegaCore Function in an Altera Device
Ease of Use
- Complete 40GbE and 100GbE examples to start your design quickly
- Register transfer level (RTL) and post-fit functional simulation for Altera supported Verilog HDL and VHDL simulators
- Testbench for simulation and hardware design examples
- Development boards
For other 40GbE and 100GbE solutions, see Altera wireline solutions.
Resource Utilization and Performance
Typical expected resource utilization and performance figures for this IP core are provided in
the 40 and 100 Gbps Ethernet MAC and PHY MegaCore Function User Guide (PDF).