Short Desc. : 40-Gbps Ethernet MAC & PHY
Overview :


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Altera offers the 40 Gbps Ethernet (40GbE) and 100 Gbps Ethernet (100GbE) MegaCore® function intellectual property (IP) cores for building systems with very high throughput-rate standard Ethernet connections. These IEEE 802.3ba-2010 40 Gbps and 100 Gbps Ethernet standard compliant media access control (MAC) and PHY (PCS+PMA) IP cores enable an Altera® device to interface to another device or to an optical transceiver module and, in turn, to 40GbE and 100GbE networks.

Figure 1 illustrates an example of Altera 40GbE or 100GbE MAC with a XLAUI, CAUI or CAUI-4 interface in an Altera device. 40GbE and 100GbE are two different IP cores.

Figure 1. 40GbE or 100GbE MegaCore Function in an Altera Device

Supported Devices


Ease of Use

Protocol Solution

For other 40GbE and 100GbE solutions, see Altera wireline solutions.

Resource Utilization and Performance

Typical expected resource utilization and performance figures for this IP core are provided in
the 40 and 100 Gbps Ethernet MAC and PHY MegaCore Function User Guide (PDF).

Features :
  • Compliant with the IEEE 802.3ba-2010 40 Gbps and 100 Gbps Ethernet standard
  • XLAUI, CAUI and CAUI-4 physical medium attachment (PMA) hard IP and external interface consisting of serial transceiver lanes each operating at 10.3125 Gbps or 25.78125 Gbps
  • 40GbE and 100GbE physical coding sublayer (PCS) soft IP cores implemented in FPGA fabric
  • 40GbE and 100GbE MAC soft IP cores with configurable feature set
  • Supported options:
    • 40GbE or 100GbE
    • MAC+PHY, PHY-only or MAC-only
    • Transmitter plus receiver (full-duplex), transmitter-only or receiver-only
    • 100GbE PHY options: CAUI (10 x 10.3125 Gbps) or CAUI-4 (4 x 25.78125 Gbps)
  • Support full 40 Gbps and 100 Gbps wire speed traffic respectively
  • PCS bit error rate (BER) monitor
  • Programmable PCS test pattern generator and checker
  • Deficit idle count (DIC)
  • Automatic Ethernet flow control
  • Programmable MAC transmitter (TX) cyclic redundancy check (CRC) insertion and receiver (RX) CRC removal
  • Programmable maximum receive frame length up to 9,600 bytes
  • Programmable MAC address and receiver (RX) packet filtering based on MAC address
  • Promiscuous (transparent) and non-promiscuous (filtered) MAC operation modes
    • Programmable MAC received frame filtering with CRC, oversized and undersized frame error
    • Receive filtering of control frames (pause control and/or non-pause control)
  • Receive user-controllable pad removal
  • Transmit automatic pad insertion
  • Statistics status output signals for external statistics counters implementation
  • Optional 64 bit statistics counters module for RMON (RFC 2819), Ethernet-type MIB (RFC 3635), and interface group MIB (RFC 2863)
  • Programmable link fault signalling
  • Optional preamble pass through
  • Avalon® Streaming (Avalon-ST) interface for MAC data path to client application with the start of packet (SOP) in 64 bit lane0's most significant byte (MSB) when adapter option is used (100GbE: 512 bits at 312.5+ MHz; 40GbE: 256 bits at 312.5+ MHz)
    • Custom streaming interface with SOP possible on any 64 bit lane MSB when adapter option is not used (100GbE: 320 bits at 312.5+ MHz; 40GbE: 128 bits at 312.5+ MHz)
  • Avalon Memory Mapped (Avalon-MM) 32-bit interface for control and monitoring of MAC, PCS, PMA, and external optical module
  • Management data input/output (MDIO) or 2-wire serial interfaces for managing different optical modules
  • Passed functional and performance tests with 40/100Gb Ethernet test equipment

Categories :
Portability :
 FPGA Technologis 
Altera :
Arria 10

Type : Hard

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