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Short Desc. : 1G/10Gb Ethernet PHY
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Altera's 1G/10Gb Ethernet PHY MegaCore Function

Altera provides a complete 1 Gbps/10 Gbps Ethernet (1G/10GbE) physical coding sublayer (PCS), and physical media attachment (PMA) sublayer intellectual property (IP) known as PHY IP. This IP also supports four data rates 10M/100M/1G/10Gb referred to as 10M-10GbE. This IP is compliant to the SGMII specification at 10/100/1000 Mbps data rates, and compliant to the IEEE 802.3 Ethernet 1000BASE-X and 10GBASE-R standards at 1G/10Gbps data rates. Altera's 1G/10GbE PHY enables connectivity at 1 Gbps over 1Gb Ethernet SFP optical or copper modules and PHY devices, and over 10Gb or 1G/10Gb dual speed Ethernet SFP+ optical modules and PHY devices, and over 10/100/1000Mbps interfaces and Copper PHY devices. The 1G/10GbE Ethernet PHY MegaCore® function allows one FPGA port to be used for various interfaces, saving component cost, board space, and power. This interface PHY can be implemented in Altera® Arria® 10, Stratix® V, and Arria V GZ FPGAs with integrated and silicon-proven serial transceivers operating above 10.3125 Gbps.

Altera's 1G/10GbE PHY IP core is composed of the 1Gb and 10Gb Ethernet serial transceiver hard IP, and soft IP including an SGMII/1GE PCS, optional sequencer, control registers, and status registers for PHY management. This IP can be used for single to multiport Ethernet network interface applications for performance scalability. Altera has developed and tested in hardware the combined 1G/10Gb (10M-10Gb) Ethernet Media Access Controller (MAC) and 1G/10GbE (10M-10GbE) PHY design example.

Figure 1. 1G/10GbE (10M-10GbE) MAC and 1G/10GbE (10M-10GbE) PHY Block Diagram

Figure 1. 10-Gigabit Ethernet MAC with 10GBASE-R PHY and serial 10-Gbps XFI or SFI interface Block Diagram

Easy to Use

  • Complete 1G/10GbE and 10M-10GbE PHY solution available to start your design quickly
  • Configuration and generation by the Altera MegaWizardTM Plug-In Manager parameter editor

Robust Solution

  • Designed to IEEE 802.3 Ethernet 1000BASE-X and 10GBASE-R standards
  • Extensively validated in simulation and in hardware

Protocol Solution

Performance

Typical expected performance and resource utilization figures for this IP core are provided in the Altera Transceiver PHY IP Core User Guide (PDF).

Technical Support

For technical support on this IP core, please visit Altera mySupport online issue tracking system. You can also search for related topics on this function in the Knowledge Base.


Features :
  • Integrated SGMII / 1000BASE-X / 10GBASE-R (10M-10Gb) Ethernet PCS and PMA
  • Direct internal interface with Altera 1G/10GbE (10M-10GbE) MAC for a complete single-chip solution
  • User selectable 1G/10Gb data rates during run-time or automatic speed detection (parallel-detect) between 1Gb and 10Gb and reconfiguration by PHY IP, or data rate selection among 10/100/1000Mb with Ethernet auto-negotiation function
  • 10Gb, 1G/10GbE and 10M-10GbE (SGMII/1G/10GbE) options
  • IEEE 1588 v2 option
  • Synchronous Ethernet (Sync-E) option
    • Serial transceiver clock and data recovery (CDR) recovered clock output signal exposed to the FPGA fabric for routing to a Sync-E jitter cleaner PLL
    • Separate transmitter (TX) and receiver (RX) serial transceiver PLL reference clock inputs to allow optional external Sync-E jitter cleaner PLL to feed the cleaned clock to TX PLL reference clock input
  • Receiver-link fault status detection
  • Local serial loop-back from transmitter to receiver at serial transceiver for self test
  • High-performance internal system interfaces
    • GMII and single data rate (SDR) XGMII interfaces to 1G/10GbE (10M-10GbE) MAC, 8 bits at 125 MHz and 72 bits at 156.25 MHz respectively for data transfer
    • Altera Avalon® Memory-Mapped (Avalon-MM) 32 bit interface for slave management

Categories :
Portability :
 FPGA Technologis 
Altera :
Arria 10
ARRIA V GZ
STRATIX V GT
STRATIX V GX

Type : Hard
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