As the leading provider of 10 Gbps Ethernet (10GbE) for FPGA devices, Altera offers the XAUI PHY MegaCore® function intellectual property (IP) core for you to easily build systems with a very high throughput Ethernet connection. This XAUI PHY along with a 10GbE media access control (MAC) IP core enables an Altera® device to interface to a 10GbE network through a variety of external devices, including a 10GbE PHY device or optical transceiver module.
You can implement the XAUI PHY (excluding the PHY management functions) in hard silicon in Altera Stratix® IV (GX and GT), Stratix II GX, Arria® II GX, and Cyclone® IV GX FPGAs with serial transceivers faster than 3 Gbps. The PHY management functions are implemented in soft IP. XAUI PHY can also be implemented in soft IP form in Stratix® V , Stratix IV, Arria V, and Cyclone V FPGAs with serial transceivers. Additionally, for applications requiring 20 Gbps throughput, Altera's XAUI PHY solution can support DXAUI (4x 6.25 Gbps) implementations on Stratix IV (GX and GT) FPGAs. Figure 1 illustrates an example of XAUI PHY in Altera devices.
Figure 1. XAUI PHY in an Altera Device
Typical expected performance and resource utilization figures for this IP core are provided in the XAUI PHY Resource Utilization and Performance (PDF).