Short Desc. : 10GBase-R PHY
Overview :


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As the leading provider of 10 Gbps Ethernet (10GbE) for FPGA devices, Altera offers the 10GBASE-R PHY MegaCore® function intellectual property (IP) core for designers to easily build systems with a high throughput Ethernet connection using the fewest number of I/O pins. This 10GBASE-R PHY along with a 10GbE media access control (MAC) IP core enables an Altera® device to interface to a 10GbE network through a variety of external devices, including 10GbE PHY device or optical transceiver module.

You can implement the 10GBASE-R PHY in Altera devices with serial transceivers faster than 10 Gbps. The physical subcoding layer (PCS) is implemented in soft IP for Altera's Stratix® IV GT and Arria® V (GT and ST) and implemented as hard IP in Arria 10, Stratix V (GX, GS, and GT), and Arria V GZ FPGAs. The PHY management functions are implemented in soft IP. Figure 1 illustrates an example of 10GBASE-R PHY in Altera devices.

Figure 1. 10GBASE-R PHY in an Altera Device

Figure 1. 10GBASE-R PHY in an Altera device


  1. 10GBASE-R PCS is in soft IP for Stratix IVGT and Arria V (GT and ST) devices, an in hard IP for Arria 10, Stratix V (GX, GS, and GT) and Arria V GZ FPGAs
  2. SDR XGMII = single data rate XGMII, 72 bits at 156.25 Mbps
  3. Some SFI system channels might need EDC chip here

Easy to Use

  • Complete 10GbE 10GBASE-R PHY solution available to start your design quickly
    • Register transfer level (RTL) and post-fit functional simulation for Altera supported Verilog HDL and VHDL simulators
    • 10GbE MAC and 10GBASE-R PHY verification testbench and design example
    • Development boards
  • Configuration and generation by the Altera MegaWizardTM Plug-In Manager parameter editor

Robust Solution

  • IEEE 802.3 10GbE standard compliant, clauses 46, 49, and 51
  • Extensively validated in simulation and in hardware with standard 10GbE tester
  • Passed University of New Hampshire Interoperability Lab (UNH-IOL) 10 Gbps Ethernet MAC and PCS validation tests

Protocol Solution


Typical expected performance and resource utilization figures for this IP core are provided in the Altera Transceiver PHY IP Core User Guide (PDF).

Features :
  • Complete 10GbE 10GBASE-R PHY solution for 10.3125 Gbps serial external connection to XFI and SFI interfaces or XFP and SFP+ modules
  • PHY consisting of 10GBASE-R PCS and 10.3125-Gbps physical medium attachment (PMA), and PHY management functions
  • Direct interface with Altera 10GbE MAC for a complete single-chip solution
  • PHY integrated into hard silicon in Stratix V and Arria V GZ FPGAs with 10.3125 Gbps serial transceivers; also soft 10GBASE-R PCS available in Stratix IV GT and Arria V (GT and ST) FPGAs.
  • Direct 10.3125 Gbps serial connection for chip-to-chip, chip-to-optical module, chip-to-PHY device, and backplane applications
  • Dynamic partial reconfigurable I/O (DPRIO) support in serial transceivers to adapt to various 10GBASE-R channel characteristics and devices in systems during operation
  • Implementing the Ethernet standard 10GBASE-R PHY functions: 64b/66b encoding or decoding, scrambling/descrambling, receiver rate matching for clock frequency compensation, 66b/16b gear-boxing, and data serialization or deserialization to and from 10.3125 Gbps line
  • Receiver-link fault status detection
  • Local serial loop-back from transmitter to receiver at serial transceiver for testing
  • IEEE 1588 v2 option for high precision and accuracy time stamping
  • High-performance internal system interfaces

Categories :
Portability :
 FPGA Technologis 
Altera :
Arria 10

Type : Hard
S2C: FPGA Base prototyping- Download white paper

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