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Short Desc. : 10 Gbps Ethernet MAC with 1588
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As the leading provider of 10 Gbps Ethernet (10GbE) for FPGA devices, Altera offers the 10GbE MegaCore® function intellectual property (IP) core for building systems with very high throughput Ethernet connection. This 10GbE media access control (MAC) along with a XAUI (4 x 3.125 Gbps) PHY, 10GBASE-R (10.3125 Gbps) PHY, or 10GBASE-KR (Backplane Ethernet) PHY IP core enables an Altera® device to interface to an external 10GbE PHY device or optical transceiver module and, in turn, to a 10GbE network, or directly over Copper backplane to another Backplane Ethernet device.

You can implement the XAUI (4 x 3.125 Gbps) PHY interface in Altera FPGAs with 3.125 Gbps serial transceivers, the 10GBASE-R (10.3125 Gbps) PHY interface to XFI or SFP+ modules with Altera Stratix® IV GT, Stratix V (GX, GS, and GT), Arria® V (GT, GZ, and ST), Arria 10 FPGA 10.3125 Gbps serial transceivers, and the 10GBASE-KR (10.3125 Gbps) PHY interface for Backplane Ethernet with Altera Arria 10, Stratix V, and Arria V GZ FPGAs.

The 10GbE MAC IP supports single speed 10Gb operation, and the 1G/10GbE and 10/100M/1G/10GbE (10M-10GbE) multi-speed options which allow you to build a flexible Ethernet port to connect to 10GbE or multi-data rate 10/100/1000MbE or 1G/10GbE external devices, optical modules or copper PHY devices, or directly to a copper backplane. The full Ethernet interface can be implemented with Altera 10M-10GbE MAC and SGMII / 1000BASE-X / 10GBASE-R (10M-10GbE) PHY IP or with 10GBASE-KR PHY backplane Ethernet IP. 10M-10GbE PHY IP supports 10/100/1000Mb operation with SGMII interface. This solution is supported in Arria 10, Stratix V and Arria V GZ FPGAs.

10GbE MAC with 10GBASE-R PHY, and 10M-10GbE MAC with 10M-10GbE PHY support the IEEE 1588 v2 high accuracy and high precision time stamping option in hardware. This feature facilitates standards-based accurate time and frequency synchronization to a network grand master. The 10GbE 1588 feature is supported in Stratix V (GX, GT, GS) and Arria V (GT, GZ) FPGAs. The 10M-10GbE 1588 feature is supported in Arria10, Stratix V, and Arria V GZ FPGAs.

Figures 1, 2, and 3 illustrate examples of Altera 10GbE MAC in different Altera devices with XAUI, XFI/SFI, or XGMII interfaces, respectively.

Figure 1. 10GbE MAC in an Altera Device with XAUI Interface

Figure 1. 10-GbE MAC in an Altera device with XAUI interface

Notes:

  1. SDR XGMII = single data rate (SDR) XGMII (72 bits at 156.25 Mbps)
  2. XAUI physical coding sublayer (PCS) is implemented in hard IP in Stratix IV (GX, GT), Stratix II GX, Arria II GX, and Cyclone® IV GX FPGAs, and implemented in soft IP in Arria 10, Stratix V (GX, GS, and GT), Arria V, and Cyclone V FPGAs with serial transceivers
  3. Avalon® Streaming (Avalon-ST) interface single-clock FIFO use is optional
  4. Avalon Memory-Mapped (Avalon-MM) bridge is a Qsys component

Figure 2. 10GbE MAC in an Altera Device with XFI or SFI 10G Serial Transceiver

Figure 2. 10-GbE MAC in an Altera device with XFI or SFI 10-Gbps serial transceiver

Notes:

  1. Some 10.3 Gbps SFI system channels may need EDC chip here
  2. 10GBASE-R PCS is implemented in soft IP in Stratix IV GT and Arria V (GT) FPGAs, but is implemented in hard IP for Arria 10, Stratix V (GX, GS, and GT), and Arria V GZ FPGAs
  3. Avalon-ST interface single-clock FIFO use is optional
  4. I2C Controller IP can be licensed from Altera IP partners

Figure 3. 10GbE MAC in an Altera Device with XGMII Parallel Interface

Figure 3. 10-GbE MAC in an Altera device with XGMII parallel interface

Notes:

  1. SDR XGMII = single Data Rate XGMII (72 bits at 156.25 Mbps)
  2. Avalon-ST interface single-clock FIFO use is optional.

Ease of Use

  • Complete 10GbE protocol solution available in design examples to start your design quickly
    • RTL and post-fit functional simulation for Altera supported Verilog HDL and VHDL simulators
    • Verification testbench and hardware design examples
    • Development boards
  • Configuration and generation by Altera MegaWizardTM Plug-in Manager parameter editor
  • Easy system integration with Qsys software

Robust Solution

  • IEEE 802.3 10GbE MAC standard compliant, Clauses 4, 31, and 46
  • 10M-10Gb Ethernet feature option compliant with SGMII and IEEE 802.3 1000BASE-X and 10GBASE-R, and 10GBASE-KR PCS and PMA Standards
  • 1588 feature option compliant with IEEE 1588 v2 Standard-2008
  • Extensively validated in simulation and in hardware with standard 10GbE tester
  • Passed University of New Hampshire Interoperability Lab (UNH-IOL) 10 Gbps Ethernet MAC and PCS validation tests

Protocol Solution

Performance

Typical expected resource utilization and performance figures for this IP core are provided in the 10 Gbps Ethernet MAC MegaCore Function User Guide (PDF).


Features :
  • 10GbE MAC IP
  • Interfaces directly to external devices or optical modules with Altera's integrated standard XAUI PHY (4 x 3.125 Gbps), 10GBASE-R PHY (10.3125 Gbps), 10GBASE-KR PHY, SGMII / 1000BASE-X / 10GBASE-R PHY, or XGMII (32 x 312.5 Mbps)
  • Deficit idle count (DIC)
  • Local and remote fault signaling
  • Automatic Ethernet flow control
  • Programmable maximum receiving frame length up to 16 KB including jumbo frames
  • Promiscuous (transparent) and non-promiscuous (filtered) operation modes
  • Programmable MAC addresses and receive packet filtering based on MAC addresses
  • Programmable received frame filtering with cyclic redundancy check (CRC), length check, or oversized frame error
  • 10M-10GbE multi-speed option with run-time user data rate selection
  • IEEE 1588 v2 high accuracy and high precision time stamping option in hardware IP
    • 1-step and 2-step time sync
    • Supports IEEE 1588 v2 PTP packet encapsulation in IPv4, IPv6 and Ethernet
    • Real time of day clock generator (TOD) IP in design example
  • Support for virtual LAN (VLAN) and stacked VLAN tagged frames according to the IEEE 802.1Q and 802.1ad (Q-in-Q) standards, respectively
  • Statistics counters for RMON (RFC 2819), Ethernet-type MIB (RFC 3635), and interface group MIB (RFC 2863)
  • High-performance internal system interfaces
    • Altera Avalon-ST (PDF) 64 bit at 156.25 Mbps for data transfer to and from user application logic
    • Altera Avalon-MM (PDF) 32 bit for slave management
    • Altera Avalon-ST (PDF) SDR XGMII, 72 bit at 156.25 Mbps for data transfer to and from PHY IP core
  • Complete design examples

Categories :
Portability :
 FPGA Technologis 
Altera :
Arria 10
ARRIA V GT
ARRIA V GZ
STRATIX V GT
STRATIX V GX

Type : Hard
CST Webinar Series
S2C: FPGA Base prototyping- Download white paper



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