Implements an Inter-Integrated Circuit (I2C) Bus master controller that meets the Phillips I2C, version 4.0 specification for single master I2C buses.
The I2C-M allows dynamic control of the serial clock frequency, and the I2C bus speed is only limited by the external bus driver capabilities and the frequency used to clock the core. It supports a 7- or 10-bit slave address and allows the Acknowledge cycle to be controlled by either the slave or the master. This enables operation in all bus speed modes provisioned by version 4.0 of the standard, including the unidirectional Ultra Fast Speed. Furthermore, the core is suitable for implementing the master node for I2C-based protocols, such as SMBUS, PMBUS and VESA Display Data Channel (DDC).
Under its default configuration, the I2C-M provides access to its 8-bit-wide status and control registers via an APB-slave port. Alternatively, the core can be equipped with an AHB-slave, Wishbone-slave, or generic microcontroller interface.
Controlled by a compact and comprehensive set of commands and accompanied by a low-level C-driver, the I2C-M core enables easy and rapid development of over-I2C, or I2C-like protocols in user applications. The configurable size FIFOs for read-data and commands and a rich set of interrupts help reduce host processor overhead and interaction.
The I2C-M is production-proven in ASIC and FPGA technologies.