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 Synopsys 
Part Number : dwc_arc_em6_core
Short Desc. : ARC EM6 32-bit processor core with cache for embedded applications
Overview :
Synopsys' DesignWare ® ARC® EM6 processor core is based on the next-generation ARCv2 Instruction Set Architecture (ISA) and pipeline. With support for up to 32K of instruction and data cache, the DesignWare ARC EM6 core is optimized for use in embedded and deeply embedded applications that are power- and cost-sensitiv e such as memory cards, SSD controllers, power management, portable media players and other mobile devices. The DesignWare ARCv2 architecture is a combined 16-/32-bit ISA that is compatible with the existing ARCv1 architecture used on the ARC 600 and 700 families. The ARCv2 ISA is implemented with a new scalable pipeline that enables the development of advanced RISC microprocessor cores with the optimum balance of performance, power consumption and size for a broad range of applications, giving designers a complete processor solution for their system-on-chip (SoC) designs. The DesignWare ARC EM6 processor core supports separate instruction and data L1 cache memory spaces that can be independently configured for 2K, 4K, 8K, 16K or 32K size. The instruction and data cache can be set up by the user at build time to support 1-, 2- or 4-way set associativity, and a line size of 16, 32, 64 or 128 bytes. The caches can be individually configured to support line locking and invalidate, and to offer debug visibility. The ARC EM6 has low-latency pipeline that is optimally balanced to deliver superior performance efficiency (DMIPS/mm2 and DMIPS/mW). The ARC EM6 processor core features native AHB, AHB-lite and BVCI interfaces to enable high system throughput. The core is fully supported by a complete suite of development tools, including the acclaimed MetaWare Development Kit that generates highly efficient code, the ARC simulators including xCAM and xISS, and the ARChitect ® configuration tool.
Features : - A highly configurable architecture allows SoC designers to include only the processor features that are required for their specific application, resulting in smaller die size and lower power than can be achieved with a fixed core.
- User-defined instruction and register extensions deliver 5-100 times performance improvement of critical routines.
- 16-/32-bit Instruction Set Architecture for the smallest code size
- JTAG debug port and optional embedded hardware breakpoints facilitate software debug
Categories :
Maturity : Available on request
Portability :
Type : Soft
DownStream: Solutions for Post Processing PCB Designs
S2C: FPGA Base prototyping- Download white paper
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