Part Number : dwc_ufs_host_controller
Short Desc. : UFS Host Controller and MIPI UniPro Controller
Overview :
The DesignWare ® UFS Host Controller IP is a standard based serial interface engine for implementing a JEDEC UFS interface in compliance with the JEDEC UFS Architecture Specification (UFS) and the JEDEC UFS Host Controller Specification (UFSHCI). The UFS host controller is a high-performance interface that is pri marily used in mobile devices where data is stored on non-volatile mass storage memory devices. The UFS host controller integrates the UFS host controller application layer with a pre-configured DesignWare MIPI UniPro protocol stack that is optimized for UFS host applications. When combined with the multi-gear DesignWare MIPI M-PHY IP, Synopsys provides a single vendor MIPI IP solution, enabling designers to easily integrate the UFS host implementation in application processors with less risk, while speeding time-to-market.
Features : - Enables maximized DMA throughput
- Pre-configured for up to 32 task requests and up to 8 task management requests
- Ability to perform commands without system host intervention
- Support for the full range of UPIU packets, from 32 byte to 64 kB
- Efficient interface for system host programming access and DMA controlled data transfer
- Configured as AXI or OCP interface as System bus
- Fully synchronous synthesizable RTL
- Clock gating-ready design and DFT ready
- High-performance and reliable connection to a UFS device with DesignWare MIPI M-PHY IP
- Direct support for a UniPro-compliant link layer
Categories :
Maturity : Available on request
Portability :
Type : Soft
Deliverables : - coreConsultant tool for single IP configuration, synthesis and simulation (GUI or batch scripts)
- Source Verilog RTL
- Automated synthesis using coreAssembler/coreConsultant, including support for DFT insertion and low power synthesis
- Comprehensive databook covering features, configuration, integration, software programmers guide and coreAssembler tutorial

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