Part Number : dwc_pci_express_to_amba_3_axi_bridge
Short Desc. : Bridge Core for PCI Express to AMBA 3 AXI
Overview :
The DesignWare ® IP for PCI Express® to AMBA® 3 AXI™ Bridge Core (PCIe®-AXI Bridge) enables designers who use the AMBA 3 AXI on-chip bus to easily add PCI Express external connectivity to their AMBA 3 AXI based System-on-Chip (SoC) devices. The high-quality PCIe-AXI Bridge is compliant to the latest PCI-SIG® and AMBA specifications and has been extensively validated with multiple HW platforms and verification suites. The silicon-proven PCIe-AXI Bridge works in conjunction with the complete portfolio of DesignWare Cores for PCI Express including Endpoint, Root Complex and Dual Mode and has been successf ully implemented in a wide range of applications that require demanding high-bandwidth, low latency designs.
Features : - AXI Master and slave interfaces for inbound and outbound PCI Express requests
- Supports full PCI Express configuration, I/O requests, traffic class (EP, TD, etc.) through PCIe-AXI
- Programmable buffer sizes for AXI master and slave requests and response queuing
- Independent configuration of bus width for PCI Express core data bus, AXI master bus and AXI slave bus
- Programmable AXI master and slave address widths, data bus widths, and ID bus widths
- All burst-sizes supported for both AXI master and slave interfaces
- Supports response AXI slave request gathering from split PCI Express completions
- Supports response AXI master request gathering from multiple AXI responses
- Supports response error mapping between PCI Express errors (UR, CA, CRS, poisoned, and ECRC error) and AXI slave response errors (SLVERR and DECERR) and AXI master response errors (DECERR_W and DECERR_R)
- Embedded DMA
Categories :
Maturity : In Production
Portability :
Type : Soft
Deliverables : - coreConsultant utility to guide you through the installation, configuration, verification, and implementation of the core
- Verilog RTL
- ASIC and FPGA synthesis scripts
- Core verification environment and DesignWare Verification IP for PCI Express
- Documentation: Release notes, Installation/integration guide, Application notes, User Manual
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: IoTPLL

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