The DesignWare enhanced Universal DDR controller (uMCTL2) offers a single port Host Interface. the uMCTL2 is capable of controlling JEDEC standard DDR2, DDR3, Mobile DDR and/or LPDDR2 SDRAMs. The uPCTL delivers efficient bandwidth with minimum latency and provides the designers with transparent access and complete control of the memory subsystem. The uPCTL serves the memory control needs of applications with simple transactions that do not require an internal scheduler, and can also be deployed with custom-designed memory management units. The uPCTL SoC application bus interface supports a lowest-latency " native application interface " (NIF). The uMCTL is an advanced multi-port memory controller which accepts memory access requests from up to 32 application-side host ports. Application-side interfaces can be connected to the uMCTL either through the standard AMBA AXI/AHB bus interfaces. The uPCTL is instantiated within the uMCTL. The functionality of the uMCTL is a superset of the uPCTL. Both Universal DDR controllers (uPCTL and uMCTL) connect to DDR PHY via a DFI 2.1 interface to create a complete memory interface and control solution. Both controllers include software configuration registers, which are accessed through an AMBA 2.0 APB interface.