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 Synopsys 
Part Number : dwc_sata6gphy_umc40lp_x1
Short Desc. : SATA 6G PHY, UMC 40LP, x1
Overview :
Synopsys' DesignWare ® SATA PHY IP is designed for use in system-on-chip (SoC) solutions. The DesignWare SATA PHY IP integrates seamlessly with Synopsys' DesignWare SATA Host & Device Controller IP core to reduce design time and achieve first-pass silicon success. Based on Synopsys' proven high-speed SERDES technology, the DesignWare SATA PHY IP provides a cost-effective and low power solution that is designed to meet the needs of today's SATA designs. Synopsys' SATA PHY IP is compliant with the SATA base specification and substantially exceeds the electrical specifications in such key performance areas as jitter and receive sensitivity. The SATA PHY is part of the complete DesignWare IP solution for SATA including SATA Host, Device Controller and SATA verification IP. The solution has passed the SATA-IO Building Block Interoperability Testing, the golden standard of compliance to the SATA Specification.
Features : - Fully compliant and silicon proven in popular 130nm to 40nm processes
- Passes SATA IO Interoperability testing using PHYs in 130nm to 40nm process technology
- Supports a wide range of configurations including 1.0V, 1.2V & 1.8V core supplies and 2.5V & 3.3V I/O supplies
- Transmits and receives 1.5 Gb/s or 3.0 Gb/s differential NRZ serial stream
- Excellent performance margin and receive sensitivity
- On board scope and diagnostics for fast system verification
- Interoperability with Synopsys' DesignWare SATA Host & Device Controllers to provide a complete solution
- Support for hot pluggable devices
- Low power design supports " Green " low power products
- SATA-IO Building Block Interoperability Tested
Categories :
Maturity : Available on request
Portability :
Type :
 Hard IP 
Foundry :
UMC
Nodes :
40nm
Process :
LP

Deliverables : - GDSII layout and layer map files, LEF of pin size and locations, LVS netlist in HSPICE format and LVS report, DRC report
- Simulation model for digital blocks, Behavioral models for analog blocks
- Synopsys ’ PrimeTime STA results, Gate-level netlist and SDF timing file
- DesignWare PHY Hard Macro Databook for SATA
- BSDL files for JTAG AC/DC Boundary Scan, ATE test vectors
CST Webinar Series
S2C: FPGA Base prototyping- Download white paper



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