Part Number : dwc_usb_hsic_phy-tsmc_28hpm18ns
Short Desc. : USB HSIC PHY - TSMC 28HPM18, North/South (vertical) poly orientation
Overview :
Synopsys provides designers with silicon-proven, configurable DesignWare & reg; USB 2.0 Controllers that are compliant with the USB-Implementers Forum (USB-IF) USB 2.0 specifications. The DesignWare digital controllers provide: the lowest gate count; power management optimized with dual power rails and a ULPI interface for discrete PHYs and UTMI/UTMI+ interface for integrated PHYs. This comprehensive solution includes the USB 2.0 LPM-HSIC, OTG, Host and Device Controllers. The DesignWare USB 2.0 IP is the most certified IP solution in the industry. With over 2,000 design wins and hundreds of millions of silicon-proven units shipped, Synopsys' complete USB IP solution, consisting of digital controllers, PHY and Verification IP, enables designers to lower integration risk and speed time-to-market.
Features : - Supports HSIC version 1.1
- Supports USB 2.0 Link Power Management Addendum to Universal Serial Bus Specification, Revision 2.0
- Supports 1.2V LVCMOS signaling
- Supports USB 2.0 Link Power Management Addendum to Universal Serial Bus Specification, Revision 2.0
- Integrated PHY includes transmitter, receiver, digital core, ESD, and 480 Hz PLL
- Low area
- Low Power
- HS Transmit
Categories :
Maturity : Available on request
Portability :
Type :
 Hard IP 
Foundry :
Nodes :
Process :

Deliverables : - GDSII layout and layer map files, LEF of pin size and locations, LVS netlist in HSPICE format and LVS report, DRC report
- Simulation model for digital blocks, Behavioral models for analog blocks
- Synopsys ’ PrimeTime STA results, Gate-level netlist and SDF timing file
- DesignWare USB HSIC PHY Databook
- Digital test vectors (.wgl); scan test environment with Automatic Test Pattern Generation (ATPG) vectors
DownStream: Solutions for Post Processing PCB Designs
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: UltraPLL

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