Part Number : dwc_usb3phy_otg-tsmc28hpm-x1ns
Short Desc. : USB 3.0 PHY-TSMC 28HPM18 x1 OTG, North/South Poly Orientation
Overview :
The DesignWare ® SuperSpeed USB IP complete solution is based on the USB 3.0 specification from the USB Implementers Forum and consists of the xHCI host and device controllers, PHY and verification IP. Additionally, the solution includes a SuperSpeed USB virtual platform and drivers to aid software development. U tilizing elements from a single vendor enables designers to quickly create SuperSpeed USB-based designs from concept through implementation and software development. Next generation applications, such as camcorders, portable media players and smartphones require higher bandwidth for faster " sync-and-go " functionality between PCs and portable electronic devices. SuperSpeed USB delivers more than 10x the data transfer rate of Hi-Speed USB and is backwards compatible with previous USB technologies, offering the same ease-of-use and plug-and-play capabilities, while maintaining interoperability with existing USB products. The USB 3.0 solution now includes a protocol analyzer for use with the Synopsys USB 3.0 verification IP.
Features : - Comprehensive IP solution including xHCI host and device controllers, PHY, verification IP, virtual platform and drivers
- Supports SuperSpeed USB (USB 3.0) and Hi-Speed USB (USB 2.0)
- Implements low power features such as dual power rails and Unified Power Format features to maximize battery life for portable electronics
- SuperSpeed USB 3.0 transaction-level models (TLM) enable pre-RTL & pre-silicon software development, verification & architecture exploration months before hardware & FPGA prototype
- Verification IP quickly verifies connectivity between the integrated IP and the SoC
- SuperSpeed USB IP offering from the #1 provider of USB IP for seven years in a row (Gartner Dataquest 2008)
Categories :
Maturity : Available on request
Portability :
Type :
 Hard IP 
Foundry :
Nodes :
Process :

Deliverables : - GDSII layout and layer map files, LEF of pin size and locations, LVS netlist in HSPICE format and LVS report, DRC report
- Simulation model for digital blocks, Behavioral models for analog blocks
- Synopsys ’ PrimeTime STA results, Gate-level netlist and SDF timing file
- DesignWare USB 3.0 PHY Databook
- Digital test vectors (.wgl); scan test environment with Automatic Test Pattern Generation (ATPG) vectors
S2C: FPGA Base prototyping- Download white paper

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