Login
 IP's Search 
 
 
PortabilityShow All
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
Only
 Search Result 
Displaying 2901-3000/6842

Interlaken, 100G for 28nm devices
Interlaken, 100G, 12 Lanes
Interlaken, 100G, 20 Lanes
Interlaken, 150G, 24 Lanes
Interlaken, 40G, 8 Lanes
Interlaken, 50G for 28nm devices
Interlaken-PHY (ILKN-PHY)
Features
Interleaver / De-interleaver
Features
Interleaver/De-Interleaver
Features
Inventra CON-DEC, Concatenated Decoder; ~5,700 gates documented (user parameterised design), size and max clock depends on technology and symbol rate and channe
Inventra CON-ENC, Concatenated Encoder; 15,000 - 48,000 gates (user parameterised design), size and max clock depends on technology, symbol rate and channel par
Inventra DCT-8X8, 8X8 Discrete Cosine Transform; 20,000-34,000 gates (user parameterised design), up to 160 MHz
Inventra DMAXN, Multi-Channel DMA Controller; 2,000+ gates (configurable), max clock depends on technology and number of channels.
Inventra DSP-DDS, Direct Digital Synthesizer Core; 1,500 gates, 50MHz
Inventra E1-DFRM, E1 Deframer; 1,300 gates, 90Mhz
Inventra E1-KIT-R, E1 Framing/Deframing Kit (Re-Ordering Add/Drop); 13,800 gates, 90MHz
Inventra E1-KIT-S, E1 Framing/Deframing Kit (Selective Add/Drop); 8,200 gates, 90MHz
Inventra FBUS-LIB-F, FISPbus Foundation Library; 100+ gates (configurable), 100Mhz+
Inventra FEMI, FISPbus External Memory Interface; 8,500 gates (configurable), 75Mhz
Inventra FFT, Fast Fourier Transform, Inverse FFT/Fast Convolver; 20,000 gates typical (user parameterised design), size and max clock depends on technology and
Inventra FIR, Linear Phase FIR Filter; 5,000-65,000 gates typical (user parameterised design), size and max clock depends on technology and filter order.
Inventra G711-CMP, G.711 PCM Compressing Function; 500 gates
Inventra G711-EXP, G.711 PCM Expanding Function; 500 gates
Inventra G726-COMx1, Single Channel G.726 ADPCM Compact Core; 7,000 gates, 30MHz
Inventra G726-COMxN, Multi-Channel G.726 ADPCM Compact Core; 8,000 gates, 50MHz
Inventra G726-LPx1, Single Channel G.726 ADPCM Low Power Core; 16,000 gates, 1MHz
Inventra G726-LPxN, Multi-Channel G726 ADPCM Low Power Core; 20,000 gates, <17MHz
Inventra GCI-IFACE, GCI Interface; 5,000-6,000 gates, 40MHz
Inventra HDLC-CORE, Single Channel HDLC Core; 1,850 gates, 20Mhz
Inventra HDLC-FIFO, Single Channel HDLC with FIFO; 9,000 gates, 20Mhz
Inventra HDLCxN, Multi-Channel HDLC Controller; <=58,000 gates, <=25Mhz
Inventra INT-DEINT, Interleaver/Deinterleaver; ~2,500 gates (user parameterised design), size and max clock depends on technology and parameters.
Inventra ISDNBRIM, Basic Rate ISDN S/T Interface Module; 5,000 gates, 15.5MHz
Inventra LILAC2, Scalable Linked List Access Controller; 5,000+ gates (configurable), max clock depends on technology and number of channels.
Inventra M1284H, IEEE 1284 Host Parallel Port; 6,500 gates, 24MHz
Inventra M146818, Real-Time Clock; 2,000 gates, max clock depends on technology
Inventra M16550A, Enhanced UART With FIFO; 11,500 gates, >1.8MHz
Inventra M16550S, Enhanced UART with FIFO and Synchronous CPU I/F; 6,800 gates, >1.8MHz
Inventra M165x50, Enhanced UART with FIFO and IrDA; 9,500 gates, >1.8MHz
Inventra M16C450, UART; 3,150 gates, >1.8MHz
Inventra M6402, Compact UART (M6402 & M8868a compatibe); 750 gates, Clock = 16x data rate
Inventra M765A78, Floppy Disk Controller; 12,000 gates, 10MHz
Inventra M8051, 8-Bit Microcontroller; 9,500 gates, max clock depends on technology
Inventra M8051EW, Fast 8-Bit Microcontroller with On-Chip Debug; 5,000 - 22,000 gates, max clock depends on technology
Inventra M8051W, Fast 8-Bit Microcontroller; 9,500 gates, max clock depends on technology
Inventra M8052, 8-Bit Microcontroller; 10,500 gates, max clock depends on technology
Inventra M82092IDE, IDE Controller, ATA-1; 13,600 gates
Inventra M82365SL, PCMCIA PC Host Interface; 17,000, 4.8 - 8.3 MHz
Inventra M82371IDE, IDE Controller, ATA-4 (UDMA/33); 29,750 gates, 33MHz
Inventra M8237A, 4 Channel DMA Controller; 6,100 gates, max clock depends on technology
Inventra M8251A, USART; 2,200 gates, Clock = 1, 16 or 64x baud rate
Inventra M8254, 3 Channel Counter/Timer; 3,000 gates, max clock depends on technology
Inventra M8255, Parallel Peripheral Interface; 1,000 gates, max clock depends on technology
Inventra M8259A, 8 Channel Interrupt Controller; 1,600 gates, max clock depends on technology
Inventra M82801IDE, IDE Controller, ATA-5 (UDMA/66); 30,000 gates, 66MHz
Inventra M8490, 5380 Compatible SCSI Interface; 1,500 gates, 30-40MHz
Inventra M85230, Enhanced Version of M85C30 Serial Comm. Controller; 17,500 gates, 32MHz
Inventra M85C30, Serial Communications Controller w/FIFOs; 17,500 gates, 32MHz
Inventra MCAN2.0, CAN2.0 Network Controller; 32,000 gates
Inventra MDDS78, Digital Data Separator for Floppy/Tape; 1,300 gates, Clock = 16x bit rate
Inventra MFDC78, PC-AT Floppy Disk Controller; 15,000 gates, 24/48 MHz
Inventra MI2C, I2C Bus Interface; 1,500 gates, 1 or 4 MHz (min)
Inventra MI2Cv2, I2C V2.0 Bus Interface; 1,500 gates, up to 34MHz
Inventra MPCI, 32 Bit 33/66 MHz PCI Peripheral Core
Features
Inventra MPCMCIA1, PCMCIA PC Card Interface; 2,500 gates, 4-16 MHz
Inventra MPM-8051, 8051 Microprocessor Peronality Module; 500 gates, 100MHz+
Inventra MPM-W8051, 8051 Warp Microprocessor Peronality Module; 500 gates, 100MHz+
Inventra MUSBFSFC, USB 1.1 Full-Speed Function Controller; 4500+ gates, 48MHz, User Configurable
Inventra MUSBHSFC, USB 2.0 High/Full Spreed Functin Controller; 11,000 + gates, 30/60 MHz, User Configurable
Inventra MUSBLSFC, USB 1.1 Low-Speed Function Controller; 5000 gates, 6MHz
Inventra NCO, Numerically Controlled Oscillator; 1,000-3,000 gates typical (user parameterised design), size and max clock depends on technology and angular res
Inventra PRSDEC, Programmable Reed-Solomon Decoder; 9,000 - 20,000 gate typical (user parameterised design), size and max clock depends on technology and parame
Inventra PRSENC, Programmable Reed-Solomon Encoder; 2,500 - 6,000 gate typical (user parameterised design), size and max clock depends on technology and paramet
Inventra RRS, Recursive Running Sum/Comb Filter; ~3,000 gates typical (user parameterised design), size and max clock depends on technology and filter order.
Inventra RSDEC, Reed-Solomon Decoder; 9,000 - 20,000 gate typical (user parameterised design), size and max clock depends on technology and parameters.
Inventra RSENC, Reed-Solomon Encoder; 2,500 - 6,000 gate typical (user parameterised design), size and max clock depends on technology and parameters.
Inventra T1-DFRM, T1 Deframer; 2,000 gates, 90MHz
Inventra T1-E1-FRM, T1/E1 Framer; 500 gates, 90MHz
Inventra T1-KIT-R, T1 Framing/Deframing Kit (Re-Ordering Add/Drop); 13,800 gates, 90MHz
Inventra T1-KIT-S, T1 Framing/Deframing Kit (Selective Add/Drop); 8,700 gates, 90MHz
Inventra V42BIS, V.42bis Compression Engine; 15,900 gates, 80MHz
Inventra VC, Voice Codec; 15,000 gates, 3MHz
Inventra X50-RX, X.50 Multiplexing Receiver; 1,250, 50MHz
Inventra X50-TX, X50 Multiplexing Transmitter; 375 gates, 50MHz
Inventra™ M16x50 Enhanced UART with FIFOs & IrDA Support
Features
Inventra™ M8051 8-Bit Microcontroller
Features
Inventra™ MCAN2 CAN 2.0 Network Controller
Features
Inventra™ MPCI32 32bit 33/66MHz PCI Core w/Cardbus support
Features
InvisiPHY
Features
IP Compiler for PCI Express (Hard IP)
Features
IP Compiler for PCI Express x1 (Soft IP)
Features
IP Compiler for PCI Express x4 (Soft IP)
Features
IP Compiler for PCI Express x8 (Soft IP)
Features
IP Core implements the error-correcting coding I.6 LDPC super FEC code code for the ITU-T G.795.1 recommendation
I.6 LDPC Codec
IP for DisplayPort 1.3 TX Controller
IP8540
Features
IP for Embedded DisplayPort 1.4 TX Controller
IP8542
Features
IP PCIe EZDMA2 for Xilinx FPGA
Features
IP PCIe QuickPCIe Expert for Xilinx FPGA
Features
IP PCIe2.0 EZDMA2 for Altera FPGA
Features
IP Prototyping Kit for DWC DDR uMCTL2 Controller on HAPS-DX7, DDR3/2 FPGA PHY, AXI tunnel to ARC SDP
dwipk_umctl2_eddr3phy_arc
Features
Displaying 2901-3000/6842
CST Webinar Series
Verific: SystemVerilog & VHDL Parsers
TrueCircuits: IoTPLL



Internet Business Systems © 2016 Internet Business Systems, Inc.
595 Millich Dr., Suite 216, Campbell, CA 95008
+1 (408)-337-6870 — Contact Us, or visit our other sites:
AECCafe - Architectural Design and Engineering TechJobsCafe - Technical Jobs and Resumes GISCafe - Geographical Information Services  MCADCafe - Mechanical Design and Engineering ShareCG - Share Computer Graphic (CG) Animation, 3D Art and 3D Models
  Privacy Policy