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Displaying 201-300/369

iniG704-E1
Features
INT 1020 Giga-bit Multi-port Switch
Features
Int-11500
Features
Integrated PCI Core
Features
Interlaken VIP
Features
IP Core implements the error-correcting coding I.6 LDPC super FEC code code for the ITU-T G.795.1 recommendation
I.6 LDPC Codec
IP Prototyping Kit for DWC DDR uMCTL2 Controller on HAPS-DX7, LPDDR4 emulation MultiPHY, AXI tunnel to ARC SDP
dwipk_umctl2_elpddr4phy_arc
Features
IP Prototyping Kit for DWC Ethernet QoS Controller on HAPS-DX7, Xilinx GTH PHY, PCIe Connection for PC
dwipk_ethrntqos_xlnxphy_pcie
Features
IP Prototyping Kit for DWC Ethernet XGMAC Controller on HAPS-DX7, Xilinx GTH and Ethernet PHY, PCIe Connection for PC
dwipk_ethrntxgmac_xlnxphy_pcie
Features
IP Prototyping Kit for DWC HDMI 2.0 Tx Controller on HAPS-DX7, HDMI 2.0 TX PHY card, AXI tunnel to ARC SDP
dwipk_hdmi20tx_txphy_arc
Features
IP Prototyping Kit for DWC MIPI CSI-2 Host Controller on HAPS-DX7, D-PHY card, AXI tunnel to ARC SDP
dwipk_csi2host_dphy_arc
Features
IP Prototyping Kit for DWC PCIe Gen 3.0 x1 Controller on HAPS-DX7, Xilinx GTH PHY, PCIe connection for PC
dwipk_pcie3ep_xlnxphy_pcie
Features
IP Prototyping Kit for DWC PCIe Gen3x1 Root Complex on HAPS-DX7, Xilinx GTH PHY, AXI tunnel to ARC SDP
dwipk_pcie3rc_xlnxphy_arc
Features
IP Prototyping Kit for DWC SATA AHCI Host on HAPS-DX7, Consumer 6 Gig PHY card, PCIe Connection for PC
dwipk_ahsata_c6gphy_pcie
Features
IP Prototyping Kit for DWC USB 3.0 Device Controller on HAPS-DX7, SuperSpeed PHY card, AXI tunnel to ARC SDP
dwipk_usb30device_ssphy_arc
Features
IP Prototyping Kit for DWC USB 3.0 Device Controller on HAPS-DX7, SuperSpeed PHY card, PCIe connection for PC
dwipk_usb30device_ssphy_pcie
Features
IP Prototyping Kit for DWC USB 3.0 Host Controller on HAPS-DX7, SuperSpeed PHY card, AXI tunnel to ARC SDP
dwipk_usb30host_ssphy_arc
Features
IP Prototyping Kit for DWC USB 3.0 Host Controller on HAPS-DX7, SuperSpeed PHY, PCIe connection for PC
dwipk_usb30host_ssphy_pcie
Features
IP Prototyping Kit for HDMI 2.0 Rx Controller on HAPS-DX7, HDMI 2.0 Rx PHY card, AXI tunnel to ARC SDP
dwipk_hdmi20rx_rxphy_arc
Features
IP Prototyping Kit for PCIe Gen2x1 Endpoint Controller on HAPS-DX7, Consumer 6 Gig PHY card, PCIe Connection for PC
dwipk_pcie2ep_c6gphy_pcie
Features
IPSEC (RFC 4303) 1Gbit IP Core
IPSEC-1G
Features
IPX-MA: Memory Arbiter
Features
IPX-SERDES : Multi Stream Data Serializer / Deserializer core
Features
IRQ Clock Crosser
IRQ Mapper
JetCCM – 1
Features
JetCCM – 2
Features
JetCCM – 3
Features
JPEG Decoder Core w/Header Processing
dwc_jpeg_decoder_hp-native
Features
JPEG-E
Features
JPEG-E
Features
JPEG-E (Baseline JPEG Encoder) Core
Features
JPEG-E-X
JPEG2000 1HD Encoder
intoPIX_IPX-JP1HD-E
Features
JPEG2000 4K DCI Plus Encoder (IPX-JP4K-Plus-E)
intoPIX_IPX-JP4K-Plus- E
JPEG2K-E
Features
JPEG2K_E
Features
LEON3
Features
LiquidMemory™
Features
LJPEG-E
Features
LJPEG-E -- Lossless JPEG Encoder Core
Features
logi3D
Features
logiAIR
Features
logiAIR
Features
logiCVC-ML
Features
logiCVC-ML
Features
logiI2S
Features
logiI2S
Features
logiMEM
Features
logiMEM
Features
logiRC
Features
logiRC
Features
logiUART
Features
logiUART
Features
Low-Power AVC/H.264 Baseline Profile Encoder Core
H264-E-BPS
Features
Low-Power AVC/H.264 Main Profile Encoder Core
H264-E-MPS
Features
LPDDR2 SDRAM Controller Core
Features
MC-ACT-6809
Features
Mem Test Analyzer Core
Features
Memory Test Core
Features
Mentor Graphics AXI Verification IP Suite - Altera Edition
Features
Mil-Std-1553 IP core
BRM1553D
Features
MIPI CSI-2 Controller Core
Features
MIPI DSI Controller Core
Features
Mixed Radix FFT
Features
MMSE MIMO Detector
Features
Mobile DDR SDRAM Controller Core
Features
Mobile SDR SDRAM Controller Core
Features
MPEG Transport Stream Multiplexing & Encapsulation Engine
MTS-E
Features
MSVD_HD
Features
Multi-Channel Direct Memory Access Controller IP Core
DMA4
Features
Multi-Port Register Files, SRAM HD Memory, and OTP Memory in a single highly- optimized solution
Memory
Features
Multi-Port_Front-End
Features
Multiple SecY IEEE 802.1ae MACsec IP Core for 1Gbit Ethernet
MACSEC-1G
Features
Multiple SecY IEEE 802.1ae MACsec IP Core for 40Gbit Ethernet
MACSEC-40G
Features
Multiplier
Features
MVDU
Features
Nios II Embedded Processor
ntTPC
Features
Numerically Controlled Oscillator Compiler
OL_H264e
Features
On-Chip FIFO Memory
OPB to PLB Bridge
Features
Parallel Flash Loader
PCI Compiler, 32-bit Master/Target
Features
PCI Compiler, 64-bit Master/Target
PCI Compiler, 64-bit Target
PCI Express AXI DMA Back-End Core
AXI DMA Back-End Core
Features
PCI Express Core
Expresso 3.0 Core
Features
PCI Express DMA Back-End Core
DMA Back-End Core
Features
PCI Express DMA Core
Expresso DMA Core
Features
PCI-E GEN 1/2 SerDes
Features
PCI-X Core
Features
PCIe 2.0 PHY, TSMC 16FF+LL x2, North/South (vertical) poly orientation
dwc_pcie2phy_tsmc16ffpll_x2ns
Features
PE-BB-4226 - WLAN 2x2 MIMO MAC/Baseband 802.11 ac
Features
PIP-AMBA-E -- SoC Kernel for ARM9 AMBA Bus Systems
Features
Pipelined
Features
Pipelined AES G3 for Video
AES-Video
Features
PLB to OPB Bridge
Features
PLL Interface
Features
Displaying 201-300/369
CST Webinar Series
S2C: FPGA Base prototyping- Download white paper



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